Daniël Schinkel

17 papers Journal 9Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
Compensating Processing Delay in Excess of One Clock Cycle in Noise Shaping Loops Without Altering the Filter Topology.
IEEE Access
Christiaan E. Lokin, Daniël Schinkel, Ronan A. R. van der Zee, Bram Nauta
2020 J jnl
EMI Reduction in Class-D Amplifiers by Actively Reducing PWM Ripple.
IEEE Trans. Circuits Syst. I Regul. Pap.
Christiaan E. Lokin, Ronan A. R. van der Zee, Daniël Schinkel, Bram Nauta
2018 J jnl
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.
IEEE J. Solid State Circuits
Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta
2017 — conf
5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter.
ISSCC
Fred Mostert, Daniël Schinkel, Wouter Groothedde, Lucien J. Breems, Remko van Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, Patrick Zeelen, Derk-Jan Hissink, Martin Pos, Paul Wielage, Fre Jorritsma, Marc Klein Middelink
2017 J jnl
A Multiphase Class-D Automotive Audio Amplifier With Integrated Low-Latency ADCs for Digitized Feedback After the Output Filter.
IEEE J. Solid State Circuits
Daniël Schinkel, Wouter Groothedde, Fred Mostert, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Lucien J. Breems
2015 — conf
15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise.
ISSCC
Hugo Westerveld, Daniël Schinkel, Ed van Tuijl
2010 J jnl
A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s.
IEEE J. Solid State Circuits
Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta
2010 J jnl
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects.
IEEE J. Solid State Circuits
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2009 J jnl
Low-Power, High-Speed Transceivers for Network-on-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst.
Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2008 — conf
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC.
ISSCC
Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta
2007 — conf
A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects.
ISSCC
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2007 — conf
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time.
ISSCC
Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2007 J jnl
Optimal Positions of Twists in Global On-Chip Differential Interconnects.
IEEE Trans. Very Large Scale Integr. Syst.
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2006 J jnl
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects.
IEEE J. Solid State Circuits
Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed J. M. van Tuijl, Bram Nauta
2005 — conf
An audio FIR-DAC in a BCD process for high power class-D amplifiers.
ESSCIRC
T. S. Doorn, Ed van Tuijl, Daniël Schinkel, Anne-Johan Annema, Marco Berkhout, Bram Nauta
2005 — conf
Optimally-placed twists in global on-chip differential interconnects.
ESSCIRC
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2004 — conf
Reducing quantization noise with recursive Sigma Delta modulators.
ISCAS (1)
Daniël Schinkel, Ed van Tuijl, Anne-Johan Annema