Daniel Ziener - RankMe

51 papers A 2B 5C 1Misc 6Journal 13Unranked 21

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Backing the Wrong Horse: How Bit-Level Netlist Augmentation can Counter Power Side Channel Attacks. CoRR Ali Asghar, Andreas Becher, Daniel Ziener
2025	J	`jnl`	Effective fault detection in M3D ICs: a cluster-based BIST for enhanced inter-layer via fault coverage. Frontiers Inf. Technol. Electron. Eng. Hadi Jahanirad, Ahmad Menbari, Hemin Rahimi, Daniel Ziener
2024	—	`conf`	Short Paper: Analysis of Vivado implementation strategies regarding side-channel leakage for FPGA-based AES implementations. HASP@MICRO Ali Asghar, Andreas Becher, Daniel Ziener
2022	—	`conf`	Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. ARCS Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener
2021	—	`conf`	An Energy-Efficient FPGA-based Convolutional Neural Network Implementation. SIU Hasan Irmak, Nikolaos Alachiotis, Daniel Ziener
2021	B	`conf`	Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. FPL Hasan Irmak, Daniel Ziener, Nikolaos Alachiotis
2021	—	`conf`	Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration. ARC Ali Asghar, Benjamin Hettwer, Emil Karimov, Daniel Ziener
2020	—	`conf`	A Complete Open Source Design Flow for Gowin FPGAs. FPT Pepijn de Vos, Michael Kirchhoff, Daniel Ziener
2019	—	`conf`	Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining. FPT Ali Asghar, Rick van Loo, Timon Kruiper, Daniel Ziener
2018	—	`conf`	A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks. ARCS Thorbjörn Posewsky, Daniel Ziener
2018	—	`conf`	Configuration Tampering of BRAM-based AES Implementations on FPGAs. ReConFig Daniel Ziener, Jutta Pirkl, Jürgen Teich
2018	J	`jnl`	Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems. CoRR Daniel Ziener
2018	J	`jnl`	Throughput Optimizations for FPGA-based Deep Neural Network Inference. CoRR Thorbjörn Posewsky, Daniel Ziener
2018	J	`jnl`	Throughput optimizations for FPGA-based deep neural network inference. Microprocess. Microsystems Thorbjörn Posewsky, Daniel Ziener
2017	J	`jnl`	Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. CoRR Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner
2017	J	`jnl`	Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. Integr. Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner
2016	Misc	`conf`	A LUT-Based Approximate Adder. FCCM Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich
2016	—	`conf`	Efficient deep neural network acceleration through FPGA-based batch processing. ReConFig Thorbjörn Posewsky, Daniel Ziener
2016	—	`conf`	FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener
2016	—	`ch.`	FPGA Versus Software Programming: Why, When, and How? FPGAs for Software Programmers Dirk Koch, Daniel Ziener, Frank Hannig
2016	J	`jnl`	FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber
2016	—	`book`	FPGAs for Software Programmers Dirk Koch, Frank Hannig, Daniel Ziener
2015	—	`conf`	A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich
2015	J	`jnl`	Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR Frank Hannig, Dirk Koch, Daniel Ziener
2015	—	`conf`	Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger
2014	Misc	`conf`	A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. FCCM Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener
2014	A	`conf`	An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). FPGA Bernhard Schmidt, Daniel Ziener, Jürgen Teich
2014	B	`conf`	Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich
2014	—	`conf`	Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. IPDPS Workshops Bernhard Schmidt, Daniel Ziener, Jürgen Teich
2014	J	`jnl`	Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). CoRR Frank Hannig, Dirk Koch, Daniel Ziener
2013	Misc	`conf`	Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. FCCM Christopher Dennl, Daniel Ziener, Jürgen Teich
2013	J	`jnl`	Symbolic system-level design methodology for multi-mode reconfigurable systems. Des. Autom. Embed. Syst. Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
2012	—	`conf`	FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). ReConFig Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener
2012	Misc	`conf`	On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. FCCM Christopher Dennl, Daniel Ziener, Jürgen Teich
2012	—	`conf`	Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele
2011	—	`conf`	An FPGA implementation of a threat-based strategy for Connect6. FPT Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich
2011	—	`conf`	Runtime stress-aware replica placement on reconfigurable devices under safety constraints. FPT Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich
2011	B	`conf`	Stress-Aware Module Placement on Reconfigurable Devices. FPL Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich
2011	Misc	`conf`	Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
2011	B	`conf`	Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL Stefan Wildermann, Jürgen Teich, Daniel Ziener
2010	A	`conf`	A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich
2010	—	`conf`	Multiplexing Methods for Power Watermarking. HOST Daniel Ziener, Florian Baueregger, Jürgen Teich
2010	—	`conf`	New Directions for IP Core Watermarking and Identification. Dynamically Reconfigurable Architectures Daniel Ziener, Jürgen Teich
2010	—	`—`	Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs. Daniel Ziener
2010	Misc	`conf`	Using the Power Side Channel of FPGAs for Communication. FCCM Daniel Ziener, Florian Baueregger, Jürgen Teich
2009	J	`jnl`	Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. Int. J. Auton. Adapt. Commun. Syst. Daniel Ziener, Jürgen Teich
2008	C	`conf`	Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC Daniel Ziener, Jürgen Teich
2008	—	`conf`	Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT Moritz Schmid, Daniel Ziener, Jürgen Teich
2008	J	`jnl`	Power Signature Watermarking of IP Cores for FPGAs. J. Signal Process. Syst. Daniel Ziener, Jürgen Teich
2006	—	`conf`	FPGA core watermarking based on power signature analysis. FPT Daniel Ziener, Jürgen Teich
2006	B	`conf`	Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL Daniel Ziener, Stefan Assmus, Jürgen Teich