Daniel W. Storaska

12 papers Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2025 — conf
7.2: A 2.2pJ/b 212.5Gb/s PAM-4 Transceiver with >46dB Reach in 5nm FinFET.
ISSCC
Ahmed Mostafa, A. Hassan, A. Hsu, A. K. Singh, C.-H. Wu, C.-R. Yang, D. Prabakaran, Daniel W. Storaska, D. Zhou, Davide Visani, Edmund Hsiao, F. Chu, F. Khan, Fei Lu, G. Cui, G. Wang, J. Natonio, J. Deng, J. Ding, J. Guo, J. Gu, J. Zang, L. Jiang, K.-M. Lu, Mehedi Hasan, M. Kelly, M. H. Kashani, M. Gambhir, M. R. Patoju, M. Singh, M. Shannon, M. Yang, P. Liu, P. Ramakrishna, R. Chen, R. Ho, S. N. Shahi, S. Sivakumar, S. Xu, X. Yang, X. Han, Y.-P. Su, Z. Adal, Z. Guo, Z. Li, Z. Yu, Z. Yan, H. Wang, K. Chang
2025 J jnl
A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS.
IEEE Solid State Circuits Lett.
Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla
2024 — conf
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.
VLSI Technology and Circuits
Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla
2022 — conf
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.
ISSCC
Gautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. Ramakrishna, S. Shi, S. Parker, U. Shukla, W. Kelly, W. Su, Z. Yu
2014 J jnl
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits
Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William R. Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli
2012 J jnl
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.
IEEE J. Solid State Circuits
John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman
2012 — conf
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.
ISSCC
John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman
2005 J jnl
10+ gb/s 90-nm CMOS serial link demo in CBGA package.
IEEE J. Solid State Circuits
Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna
2004 — conf
10+ Gb/s 90nm CMOS serial link demo in CBGA package.
CICC
Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna
2000 J jnl
A 7F
IEEE J. Solid State Circuits
Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman
2000 J jnl
Advanced controlling scheme for a DRAM voltage generator system.
IEEE J. Solid State Circuits
Oliver Weinfurtner, Daniel W. Storaska, Louis Hsu
1999 J jnl
A 390-mm
IEEE J. Solid State Circuits
Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, Joseph M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman