Daniel Thiele

16 papers A* 3A 3C 1Misc 2Journal 2Unranked 3

Year	Rank	Type	Title / Venue / Authors
2022	—	`—`	Formal Timing Analysis of Ethernet TSN Extensions for Automotive Applications (Formale Timing Analyse von Ethernet TSN Erweiterungen für automobile Anwendungen) Daniel Thiele
2017	J	`jnl`	A system-level FPGA design methodology for video applications with weakly-programmable hardware components. J. Real Time Image Process. Henning Sahlbach, Daniel Thiele, Rolf Ernst
2017	—	`ch.`	Networked Real-Time Embedded Systems. Handbook of Hardware/Software Codesign Haibo Zeng, Prachi Joshi, Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Petru Eles
2016	A	`conf`	Formal analysis based evaluation of software defined networking for time-sensitive Ethernet. DATE Daniel Thiele, Rolf Ernst
2016	J	`jnl`	Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks. Real Time Syst. Daniel Thiele, Johannes Schlatow, Philip Axer, Rolf Ernst
2016	C	`conf`	Formal worst-case performance analysis of time-sensitive Ethernet with frame preemption. ETFA Daniel Thiele, Rolf Ernst
2016	A	`conf`	Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper. DATE Daniel Thiele, Rolf Ernst
2016	A*	`conf`	Invited - Towards fail-operational ethernet based in-vehicle networks. DAC Mischa Möstl, Daniel Thiele, Rolf Ernst
2015	—	`conf`	Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers. VNC Daniel Thiele, Rolf Ernst, Jonas Diemer
2015	A*	`conf`	Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling. DAC Daniel Thiele, Philip Axer, Rolf Ernst
2014	A*	`conf`	Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks. DAC Philip Axer, Daniel Thiele, Rolf Ernst, Jonas Diemer
2014	—	`conf`	Formal timing analysis of automatic repeat request for switched real-time networks. SIES Philip Axer, Daniel Thiele, Rolf Ernst
2014	Misc	`conf`	Improving formal timing analysis of switched ethernet by exploiting traffic stream correlations. CODES+ISSS Daniel Thiele, Philip Axer, Rolf Ernst, Jan R. Seyler
2013	Misc	`conf`	Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet. CODES+ISSS Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Jan R. Seyler
2012	—	`conf`	Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching. SIES Jonas Diemer, Daniel Thiele, Rolf Ernst
2012	A	`conf`	Optimizing performance analysis for synchronous dataflow graphs with shared resources. DATE Daniel Thiele, Rolf Ernst