Daniel M. Dreps

13 papers A* 2Misc 1Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2018 J jnl
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI.
IBM J. Res. Dev.
Jeffrey Stuecheli, William J. Starke, John D. Irish, L. Baba Arimilli, Daniel M. Dreps, Bart Blaner, Curt Wollbrink, Brian Allison
2017 A* conf
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
MICRO
Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad
2015 J jnl
IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev.
Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
2014 — conf
5.1 POWER8
ISSCC
Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
2014 — conf
The POWER8
ICICDT
Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
2010 Misc conf
Channel Optimization for the Design of High Speed I/O links.
VLSI Design
Rohan Mandrekar, Yaping Zhou, Sungjun Chun, Anand Haridass, Jinwoo Choi, Nanju Na, Daniel M. Dreps, Roger D. Weekly, Paul Harvey
2009 — conf
A 5.4mW 0.0035mm
ISSCC
Kyu-Hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
2009 — conf
Design methodology of high performance on-chip global interconnect using terminated transmission-line.
ISQED
Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2009 J jnl
Packaging design challenges of the IBM System z10 Enterprise Class server.
IBM J. Res. Dev.
Thomas-Michael Winkel, Hubert Harrer, Dierk Kaller, Jochen Supper, Daniel M. Dreps, Kenneth L. Christian, D. Cosmadelis, Tingdong Zhou, Thomas Strach, J. Ludwig, David L. Edwards
2008 — conf
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator.
ISSCC
Kyu-Hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
2008 — conf
Low Power Passive Equalizer Design for Computer Memory Links.
Hot Interconnects
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2008 A* conf
Low power passive equalizer optimization using tritonic step response.
DAC
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng
2007 J jnl
High-speed interconnect and packaging design of the IBM System z9 processor cage.
IBM J. Res. Dev.
Hubert Harrer, Daniel M. Dreps, Thomas-Michael Winkel, Wolfgang Scholz, Bao G. Truong, Andreas Huber, Tingdong Zhou, Kenneth L. Christian, Gary F. Goth