Daniel Lustig

35 papers A* 21A 1Journal 11
YearRankTypeTitle / Venue / Authors
2023 A* conf
FinePack: Transparently Improving the Efficiency of Fine-Grained Transfers in Multi-GPU Systems.
HPCA
Harini Muthukrishnan, Daniel Lustig, Oreste Villa, Thomas F. Wenisch, David W. Nellans
2023 A conf
Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows.
CGO
Vijay Kandiah, Daniel Lustig, Oreste Villa, David W. Nellans, Nikos Hardavellas
2022 A* conf
Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product.
ISCA
Daniel Lustig, Simon Cooksey, Olivier Giroux
2021 A* conf
Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers.
ISCA
Harini Muthukrishnan, David W. Nellans, Daniel Lustig, Jeffrey A. Fessler, Thomas F. Wenisch
2021 A* conf
GPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management.
MICRO
Harini Muthukrishnan, Daniel Lustig, David W. Nellans, Thomas F. Wenisch
2021 A* conf
Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator.
HPCA
Oreste Villa, Daniel Lustig, Zi Yan, Evgeny Bolotin, Yaosheng Fu, Niladrish Chatterjee, Nan Jiang, David W. Nellans
2020 A* conf
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems.
HPCA
Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David W. Nellans
2020 J jnl
RealityCheck: Bringing Modularity, Hierarchy, and Abstraction to Automated Microarchitectural Memory Consistency Verification.
CoRR
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi
2019 A* conf
A Formal Analysis of the NVIDIA PTX Memory Consistency Model.
ASPLOS
Daniel Lustig, Sameer Sahasrabuddhe, Olivier Giroux
2019 A* conf
Nimble Page Management for Tiered Memory Systems.
ASPLOS
Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee
2019 J jnl
Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach.
IEEE Micro
Caroline Trippel, Daniel Lustig, Margaret Martonosi
2019 A* conf
Translation ranger: operating system support for contiguity-aware TLBs.
ISCA
Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee
2018 A* conf
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests.
MICRO
Caroline Trippel, Daniel Lustig, Margaret Martonosi
2018 J jnl
Full-Stack Memory Model Verification with TriCheck.
IEEE Micro
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2018 J jnl
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols.
CoRR
Caroline Trippel, Daniel Lustig, Margaret Martonosi
2018 A* conf
PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications.
MICRO
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta
2017 — book
Architectural and Operating System Support for Virtual Memory
Abhishek Bhattacharjee, Daniel Lustig
2017 A* conf
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites.
ASPLOS
Daniel Lustig, Andrew Wright, Alexandros Papakonstantinou, Olivier Giroux
2017 A* conf
RTLcheck: verifying the memory consistency of RTL designs.
MICRO
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer
2017 J jnl
Transistency Models: Memory Ordering at the Hardware-OS Interface.
IEEE Micro
Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Martonosi
2017 A* conf
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA.
ASPLOS
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2016 A* conf
COATCheck: Verifying Memory Ordering at the Hardware-OS Interface.
ASPLOS
Daniel Lustig, Geet Sethi, Margaret Martonosi, Abhishek Bhattacharjee
2016 J jnl
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings.
CoRR
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2016 J jnl
Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design.
CoRR
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2015 A* conf
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures.
ISCA
Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi
2015 A* conf
CCICheck: using µhb graphs to verify the coherence-consistency interface.
MICRO
Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2015 J jnl
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.
ACM Trans. Comput. Syst.
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer
2015 — —
Specifying, Verifying, and Translating Between Memory Consistency Models
Daniel Lustig
2015 J jnl
Verifying Correct Microarchitectural Enforcement of Memory Consistency Models.
IEEE Micro
Daniel Lustig, Michael Pellauer, Margaret Martonosi
2014 J jnl
Efficient Spatial Processing Element Control via Triggered Instructions.
IEEE Micro
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
2014 A* conf
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models.
MICRO
Daniel Lustig, Michael Pellauer, Margaret Martonosi
2013 A* conf
Reducing GPU offload latency via fine-grained CPU-GPU synchronization.
HPCA
Daniel Lustig, Margaret Martonosi
2013 J jnl
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs.
ACM Trans. Archit. Code Optim.
Daniel Lustig, Abhishek Bhattacharjee, Margaret Martonosi
2013 A* conf
Triggered instructions: a control paradigm for spatially-programmed architectures.
ISCA
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
2011 A* conf
Shared last-level TLBs for chip multiprocessors.
HPCA
Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi