Daniel J. Sorin

114 papers A* 29A 16B 14C 5Journal 36Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology. IEEE Comput. Archit. Lett. Sanya Srivastava, Fletch Rydell, Andrés Goens, Vijay Nagarajan, Daniel J. Sorin
2025	J	`jnl`	Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking. CoRR Weihang Li, Pete Crowley, Arya Tschand, Yu Wang, Miroslav Pajic, Daniel J. Sorin
2024	A*	`conf`	Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. ISCA Weihang Li, Andrés Goens, Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin
2024	J	`jnl`	Low-Energy Line Codes for On-Chip Networks. CoRR Beyza Dabak, Major Glenn, Jingyang Liu, Alexander Buck, Siyi Yang, A. Robert Calderbank, Natalie Enright Jerger, Daniel J. Sorin
2024	B	`conf`	PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model. PACT An Qi Zhang, Andrés Goens, Nicolai Oswald, Tobias Grosser, Daniel J. Sorin, Vijay Nagarajan
2023	J	`jnl`	HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. IEEE Micro Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo X. Olausson, Reece Carr
2023	A*	`conf`	Rigorous Evaluation of Computer Processors with Statistical Model Checking. MICRO Filip Mazurek, Arya Tschand, Yu Wang, Miroslav Pajic, Daniel J. Sorin
2022	A*	`conf`	HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. HPCA Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo Olausson, Reece Carr
2022	B	`conf`	Spatiotemporal Strategies for Long-Term FPGA Resource Management. ISPASS Atefeh Mehrabi, Daniel J. Sorin, Benjamin C. Lee
2021	J	`jnl`	Bayesian Optimization for Efficient Accelerator Synthesis. ACM Trans. Archit. Code Optim. Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin
2021	B	`conf`	Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. ISPASS Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor
2021	J	`jnl`	Reconfigurable Hardware in Postsilicon Microarchitecture. Computer Daniel J. Sorin
2020	—	`book`	A Primer on Memory Consistency and Cache Coherence, Second Edition A Primer on Memory Consistency and Cache Coherence (2nd Ed.) Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood
2020	J	`jnl`	Computer Architecture for Orbital Edge Computing. Computer Daniel J. Sorin
2020	A	`conf`	Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. DSN Samantha Archer, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin
2020	A*	`conf`	HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols. ISCA Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin
2020	A	`conf`	Prospector: Synthesizing Efficient Accelerators via Statistical Learning. DATE Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin
2020	A	`conf`	Roadmap Subsampling for Changing Environments. IROS Sean Murray, George Dimitri Konidaris, Daniel J. Sorin
2019	—	`conf`	A Programmable Architecture for Robot Motion Planning Acceleration. ASAP Sean Murray, Will Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin
2019	A	`conf`	GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors. DSN Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin
2018	J	`jnl`	Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin
2018	J	`jnl`	Low-Power Content Addressable Memory. Computer Daniel J. Sorin
2018	A*	`conf`	ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications. ISCA Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin
2017	A*	`conf`	Architecting hierarchical coherence protocols for push-button parametric verification. MICRO Opeoluwa Matthews, Daniel J. Sorin
2017	J	`jnl`	Correcting Two Deletions and Insertions in Racetrack Memory. CoRR Alireza Vahid, Georgios Mappouras, Daniel J. Sorin, A. Robert Calderbank
2017	C	`conf`	Jenga: Efficient Fault Tolerance for Stacked DRAM. ICCD Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin
2017	J	`jnl`	Persistent Memory. Computer Daniel J. Sorin
2016	A	`conf`	Methuselah Flash: Rewriting Codes for Extra Long Storage Lifetime. DSN Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin
2016	J	`jnl`	Profile-Driven Automated Mixed Precision. CoRR Ralph Nathan, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
2016	—	`conf`	Robot Motion Planning on a Chip. Robotics: Science and Systems Sean Murray, Will Floyd-Jones, Ying Qi, Daniel J. Sorin, George Dimitri Konidaris
2016	J	`jnl`	TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization. CoRR Blake A. Hechtman, Andrew D. Hilton, Daniel J. Sorin
2016	A*	`conf`	The microarchitecture of a real-time robot motion planning accelerator. MICRO Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin
2016	J	`jnl`	Top Picks from the 2015 Computer Architecture Conferences. IEEE Micro Milo M. K. Martin, Daniel J. Sorin
2016	B	`conf`	Verifiable hierarchical protocols with network invariants on parametric systems. FMCAD Opeoluwa Matthews, Jesse D. Bingham, Daniel J. Sorin
2015	J	`jnl`	Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores. IEEE Comput. Archit. Lett. Ralph Nathan, Daniel J. Sorin
2015	B	`conf`	Multi-program benchmark definition. ISPASS Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin
2015	J	`jnl`	PVCoherence: Designing Flat Coherence Protocols for Scalable Verification. IEEE Micro Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin
2015	J	`jnl`	Reduced Precision Checking to Detect Errors in Floating Point Arithmetic. CoRR Yaqi Zhang, Ralph Nathan, Daniel J. Sorin
2015	—	`conf`	Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design. MEMSYS Ali Eslami, Alfredo Velasco, Alireza Vahid, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin
2014	A*	`conf`	Architecting Dynamic Power Management to be Formally Verifiable. DAC Daniel J. Sorin, Opeoluwa Matthews, Meng Zhang
2014	A	`conf`	Nostradamus: Low-cost hardware-only error detection for processor cores. DATE Ralph Nathan, Daniel J. Sorin
2014	A*	`conf`	PVCoherence: Designing flat coherence protocols for scalable verification. HPCA Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin
2014	A	`conf`	Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. SC Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
2014	A*	`conf`	Scalably verifiable dynamic power management. HPCA Opeoluwa Matthews, Meng Zhang, Daniel J. Sorin
2013	C	`conf`	Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication. PRDC Kushal Seetharam, Lance Ong-Siong Co Ting Keh, Ralph Nathan, Daniel J. Sorin
2013	A*	`conf`	Coset coding to extend the lifetime of memory. HPCA Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin
2013	J	`jnl`	Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips. CoRR Blake A. Hechtman, Daniel J. Sorin
2013	B	`conf`	Evaluating cache coherent shared virtual memory for heterogeneous multicore chips. ISPASS Blake A. Hechtman, Daniel J. Sorin
2013	A*	`conf`	Exploring memory consistency for massively-threaded throughput-oriented processors. ISCA Blake A. Hechtman, Daniel J. Sorin
2013	J	`jnl`	Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point. CoRR Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
2012	J	`jnl`	Why on-chip cache coherence is here to stay. Commun. ACM Milo M. K. Martin, Mark D. Hill, Daniel J. Sorin
2012	—	`conf`	Writing cosets of a convolutional code to increase the Lifetime of Flash memory. Allerton Conference Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin
2011	—	`book`	A Primer on Memory Consistency and Cache Coherence Daniel J. Sorin, Mark D. Hill, David A. Wood
2011	J	`jnl`	Address Translation Aware Memory Consistency. IEEE Micro Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin
2011	A*	`conf`	An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2. SIGMETRICS Patrick J. Eibl, Albert Meixner, Daniel J. Sorin
2011	A	`conf`	Architectures for online error detection and recovery in multicore processors. DATE Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, Arijit Biswas, Xavier Vera
2010	A*	`conf`	Fractal Coherence: Scalably Verifiable Cache Coherence. MICRO Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin
2010	J	`jnl`	Fractal Consistency: Architecting the Memory System to Facilitate Verification. IEEE Comput. Archit. Lett. Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin
2010	A*	`conf`	Specifying and dynamically verifying address translation-aware memory consistency. ASPLOS Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin
2010	A*	`conf`	UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. HPCA Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy
2009	—	`conf`	Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms. DFT Meng Zhang, Anita Lungu, Daniel J. Sorin
2009	J	`jnl`	Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. IEEE Trans. Dependable Secur. Comput. Albert Meixner, Daniel J. Sorin
2009	A	`conf`	Dynamic power gating with quality guarantees. ISLPED Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin
2009	—	`book`	Fault Tolerant Computer Architecture Daniel J. Sorin
2009	C	`conf`	Multicore power management: Ensuring robustness via early-stage formal verification. MEMOCODE Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen
2009	—	`conf`	Reduced Precision Checking for a Floating Point Adder. DFT Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
2008	J	`jnl`	Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. IEEE Micro Albert Meixner, Michael E. Bauer, Daniel J. Sorin
2008	B	`conf`	Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. PACT Bogdan F. Romanescu, Daniel J. Sorin
2008	A	`conf`	Detouring: Translating software to circumvent hard faults in simple cores. DSN Albert Meixner, Daniel J. Sorin
2008	—	`conf`	Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. Conf. Computing Frontiers Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin
2008	J	`jnl`	The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling. IEEE Micro Fred A. Bower, Daniel J. Sorin, Landon P. Cox
2007	A*	`conf`	Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. MICRO Albert Meixner, Michael E. Bauer, Daniel J. Sorin
2007	J	`jnl`	Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown CoRR Jonathan R. Carter, Sule Ozev, Daniel J. Sorin
2007	B	`conf`	Error Detection Using Dynamic Dataflow Verification. PACT Albert Meixner, Daniel J. Sorin
2007	A*	`conf`	Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. HPCA Albert Meixner, Daniel J. Sorin
2007	—	`conf`	Lazy Error Detection for Microprocessor Functional Units. DFT Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin
2007	C	`conf`	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. ICCD Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
2007	J	`jnl`	Online diagnosis of hard faults in microprocessors. ACM Trans. Archit. Code Optim. Fred A. Bower, Daniel J. Sorin, Sule Ozev
2007	B	`conf`	Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. PACT Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev
2007	—	`conf`	Unified microprocessor core storage. Conf. Computing Frontiers Albert Meixner, Daniel J. Sorin
2007	J	`jnl`	VariaSim: simulating circuits and systems in the presence of process variability. SIGARCH Comput. Archit. News Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin
2007	B	`conf`	Verification-Aware Microprocessor Design. PACT Anita Lungu, Daniel J. Sorin
2006	—	`conf`	Applying architectural vulnerability Analysis to hard faults in the microprocessor. SIGMETRICS/Performance Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev
2006	C	`conf`	Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. ICCD Nathan Sadler, Daniel J. Sorin
2006	A	`conf`	Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. DSN Albert Meixner, Daniel J. Sorin
2006	J	`jnl`	NANA: A nano-scale active network architecture. ACM J. Emerg. Technol. Comput. Syst. Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
2006	A	`conf`	Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. ITC Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin
2006	J	`jnl`	Spin Detection Hardware for Improved Management of Multithreaded Systems. IEEE Trans. Parallel Distributed Syst. Tong Li, Alvin R. Lebeck, Daniel J. Sorin
2005	A*	`conf`	A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. MICRO Fred A. Bower, Daniel J. Sorin, Sule Ozev
2005	J	`jnl`	Autonomic Microprocessor Execution via Self-Repairing Arrays. IEEE Trans. Dependable Secur. Comput. Fred A. Bower, Sule Ozev, Daniel J. Sorin
2005	A	`conf`	Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. DATE Jonathan R. Carter, Sule Ozev, Daniel J. Sorin
2005	A*	`conf`	Dynamic Verification of Sequential Consistency. ISCA Albert Meixner, Daniel J. Sorin
2005	J	`jnl`	Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood
2005	—	`conf`	Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. USENIX ATC, General Track Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin
2005	J	`jnl`	Self-Assembled Architectures and the Temporal Aspects of Computing. Computer Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
2004	B	`conf`	Communication breakdown: analyzing CPU usage in commercial Web workloads. ISPASS Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin
2004	A	`conf`	Tolerating Hard Faults in Microprocessor Array Structures. DSN Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin
2004	A	`conf`	Using Speculation to Simplify Multiprocessor Design. IPDPS Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
2003	J	`jnl`	Analytic Evaluation of Shared-Memory Architectures. IEEE Trans. Parallel Distributed Syst. Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon
2003	A	`conf`	Dynamic Verification of End-to-End Multiprocessor Invariants. DSN Daniel J. Sorin, Mark D. Hill, David A. Wood
2003	B	`conf`	Quantifying instruction criticality for shared memory multiprocessors. SPAA Tong Li, Alvin R. Lebeck, Daniel J. Sorin
2003	J	`jnl`	Simulating a $2M Commercial Server on a $2K PC. Computer Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin
2003	A*	`conf`	Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. ISCA Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood
2002	A*	`conf`	Bandwidth Adaptive Snooping. HPCA Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood
2002	A*	`conf`	SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. ISCA Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
2002	J	`jnl`	Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Trans. Parallel Distributed Syst. Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood
2001	A*	`conf`	Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. MICRO Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti
2000	A*	`conf`	AMVA techniques for high service time variability. SIGMETRICS Derek L. Eager, Daniel J. Sorin, Mary K. Vernon
2000	A*	`conf`	Timestamp snooping: an approach for extending SMPs. ASPLOS Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood
1999	B	`conf`	A System-Level Specification Framework for I/O Architectures. SPAA Mark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin
1999	A*	`conf`	Multicast Snooping: A New Coherence Method Using a Multicast Address Network. ISCA E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood
1999	A*	`conf`	Using Lamport Clocks to Reason about Relaxed Memory Models. HPCA Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin
1998	A*	`conf`	Analytic Evaluation of Shared-memory Systems with ILP Processors. ISCA Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood
1998	B	`conf`	Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. SPAA Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill