Daniel J. Friedman

77 papers A* 1A 3C 2Misc 1Journal 30Unranked 40

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	22.2 A 16-Channel Low-Power Cryo-CMOS Flux Control Pulse Generator ASIC in 14nm FinFET Technology. ISSCC Kevin Tien, David J. Frank, John F. Bulzacchelli, Pat Rosno, Daniel Moertl, John Timmerwilke, Ari Noori, Devin Underwood, Ken Inoue, Subhajit Ray, Daniel Ramirez, Timothy J. Schmerbeck, Bryce Snell, Jeremy Ekman, Ryan Black, Mark Yeck, Tom Haselhorst, Emma Erickson, Kevin Demsky, Christian W. Baks, Jonathan Kaus, Andrea Ruffino, Pier Andrea Francese, Andy Davies, Sudipto Chakraborty, Scott Lekuch, Brian P. Gaucher, Bodhisatwa Sadhu, Scott Willenborg, Daniel J. Friedman
2025	—	`conf`	Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions. CICC Bodhisatwa Sadhu, Kevin Tien, Sudipto Chakraborty, David J. Frank, Pat Rosno, Daniel Moertl, Mark Yeck, John F. Bulzacchelli, Daniil Frolov, Devin Underwood, Ken Inoue, Christian W. Baks, Daniel Ramirez, Jeremy Ekman, Ryan Black, Timothy J. Schmerbeck, Ray Richetta, Dereje Yilma, Andrew Davies, Joseph A. Glick, Dorothy Wisnieff, Bryce Snell, John Timmerwilke, Raphael Robertazzi, George Zettles, Scott Lekuch, Scott Willenborg, Brian P. Gaucher, Daniel J. Friedman
2025	A	`conf`	Design Techniques for Ultra-low Power Cryogenic CMOS for Quantum Computing Applications. ISLPED Sudipto Chakraborty, Pat Rosno, John F. Bulzacchelli, David J. Frank, Rajiv V. Joshi, Daniel J. Friedman
2024	Misc	`conf`	Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays. VTS Raphael Robertazzi, David J. Frank, Kevin Tien, John Timmerwilke, Peilin Song, Daniel J. Friedman
2023	J	`jnl`	A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2023	—	`conf`	Cryogenic CMOS: design considerations for future quantum computing systems. CICC Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman
2023	—	`conf`	Low power cryogenic RF ASICs for quantum computing. CICC David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2022	—	`conf`	A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2022	—	`conf`	A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. ISSCC David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2022	J	`jnl`	A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. IEEE J. Solid State Circuits Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2022	A	`conf`	A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. DATE Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2022	—	`conf`	An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2021	—	`conf`	24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology. ISSCC Alexander Fritsch, Rajiv V. Joshi, Sudipto Chakraborty, Holger Wetter, Uma Srinivasan, Matthew Hyde, Otto A. Torreiter, Michael Kugel, Dan Radko, Hyong Kim, Daniel J. Friedman
2020	J	`jnl`	A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman
2020	J	`jnl`	EM-Side-Channel Resistant Symmetric-Key Authentication Mechanism for Small Devices. IACR Cryptol. ePrint Arch. Rick Boivie, Charanjit S. Jutla, Daniel J. Friedman, Ghavam G. Shahidi
2019	J	`jnl`	Crypto anchors. IBM J. Res. Dev. Venkat S. K. Balagurusamy, Cyril Cabral, Srikumar Coomaraswamy, Emmanuel Delamarche, Donna N. Dillenberger, Gero Dittmann, Daniel J. Friedman, Onur Gökçe, Nigel Hinds, Jens Jelitto, Andreas Kind, Ashwin Dhinesh Kumar, Frank Libsch, Joseph W. Ligman, Seiji Munetoh, Chandra Narayanaswami, Abhilash Narendra, Arun Paidimarri, Miguel Ángel Prada-Delgado, James T. Rayfield, Chitra K. Subramanian, Roman Vaculín
2018	—	`conf`	SC: Hardware approaches to machine learning and inference. ISSCC Daniel J. Friedman
2018	—	`conf`	Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. BCICTS Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman
2017	—	`conf`	7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. ISSCC Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia
2017	J	`jnl`	A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Mark A. Ferriss, Duixian Liu, Daniel J. Friedman, Alberto Valdes-Garcia
2017	—	`conf`	Ultra-low-power analog design. ISSCC Daniel J. Friedman
2017	C	`conf`	Very Low Voltage (VLV) Design. ICCD Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel J. Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler
2016	—	`conf`	10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. ISSCC Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
2016	J	`jnl`	A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman
2015	—	`conf`	10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. ISSCC Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
2015	J	`jnl`	A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2015	—	`conf`	A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman
2014	—	`conf`	A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2014	J	`jnl`	A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J. Solid State Circuits Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman
2014	J	`jnl`	Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. IEEE Des. Test Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu, Andreea Balteanu, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Daniel J. Friedman
2014	J	`jnl`	Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2014	A	`conf`	Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha
2013	—	`conf`	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2013	—	`conf`	A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI. CICC Mihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman
2013	C	`conf`	A linearized voltage-controlled oscillator for dual-path phase-locked loops. ISCAS Glenn E. R. Cowan, Mounir Meghelli, Daniel J. Friedman
2013	J	`jnl`	A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman
2013	J	`jnl`	Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	—	`conf`	Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2012	J	`jnl`	A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. IEEE J. Solid State Circuits Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. ISSCC Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2012	J	`jnl`	A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman
2012	—	`conf`	A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman
2012	—	`conf`	A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. CICC Jean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	A compact low-power 3D I/O in 45nm CMOS. ISSCC Yong Liu, Wing K. Luk, Daniel J. Friedman
2012	J	`jnl`	An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. IEEE J. Solid State Circuits Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman
2012	—	`conf`	An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman
2012	J	`jnl`	Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. IEEE J. Solid State Circuits John F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman
2011	—	`conf`	A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman
2010	J	`jnl`	The population health record: concepts, definition, design, and implementation. J. Am. Medical Informatics Assoc. Daniel J. Friedman, R. Gibson Parrish II
2009	J	`jnl`	A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. IEEE J. Solid State Circuits Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
2009	—	`conf`	A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. ISSCC Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
2009	J	`jnl`	A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. IEEE J. Solid State Circuits Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
2009	—	`conf`	A 5.4mW 0.0035mm ISSCC Kyu-Hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
2009	—	`conf`	A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. ISSCC John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman
2009	—	`conf`	Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman
2008	—	`conf`	A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. ISSCC Kyu-Hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
2008	—	`conf`	A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman
2008	J	`jnl`	A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. IEEE J. Solid State Circuits José A. Tierno, Alexander V. Rylyakov, Daniel J. Friedman
2008	—	`conf`	A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. CICC Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman
2007	J	`jnl`	A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. IEEE J. Solid State Circuits Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman
2007	—	`conf`	A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver. ISSCC Matt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman
2007	—	`conf`	A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. ISSCC Alexander V. Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli
2007	—	`conf`	All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. ISSCC Yong Liu, Woogeun Rhee, Daniel J. Friedman, Donhee Ham
2007	J	`jnl`	An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. IEEE J. Solid State Circuits Babak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget
2006	J	`jnl`	A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
2006	—	`conf`	A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
2006	—	`conf`	An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback. CICC Baharak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget
2006	J	`jnl`	Phase and amplitude pre-emphasis techniques for low-power serial links. IEEE J. Solid State Circuits James F. Buckwalter, Mounir Meghelli, Daniel J. Friedman, Ali Hajimiri
2004	J	`jnl`	A semi-digital delay-locked loop using an analog-based finite state machine. IEEE Trans. Circuits Syst. II Express Briefs Woogeun Rhee, Benjamin D. Parker, Daniel J. Friedman
2003	—	`conf`	45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. CICC Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander V. Rylyakov, Young Hoon Kwark, Daniel J. Friedman
2003	J	`jnl`	A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. IEEE J. Solid State Circuits Mounir Meghelli, Alexander V. Rylyakov, Steven Zier, Michael Sorna, Daniel J. Friedman
2003	—	`conf`	A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. CICC Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer
2003	J	`jnl`	SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer
1991	A*	`conf`	VLSI sensori-motor systems. ICRA James J. Clark, Daniel J. Friedman