Daniel Große - RankMe

212 papers A* 10A 36B 11C 39Misc 2Journal 28Unranked 81

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture. ASP-DAC Manfred Schlägl, Andreas Hinterdorfer, Daniel Große
2026	—	`conf`	QSOLE: Automatic QBF Equivalence Checking. TACAS (1) Peter Pfeiffer, Mark Peyrer, Daniel Große, Martina Seidl
2026	J	`jnl`	SonicRV: An Educational Platform for Web-Based Simulation and Visualization of RISC-V Processor Architectures. IEEE Access Daniel Große, Simon Reitinger, Lucas Klemmer
2025	C	`conf`	Boosting SW Development Efficiency with Function Lifetime Diagrams. DDECS Christoph Hazott, Daniel Große
2025	C	`conf`	Control Flow Protection by Cryptographic Instruction Chaining. SECRYPT Shahzad Ahmad, Stefan Rass, Maksim Goman, Manfred Schlägl, Daniel Große
2025	J	`jnl`	Divider verification using symbolic computer algebra and delayed don't care optimization: theory and practical implementation. Formal Methods Syst. Des. Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2025	A	`conf`	Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes. DATE Manfred Schlägl, Daniel Große
2025	C	`conf`	LLM-assisted Metamorphic Testing of Embedded Graphics Libraries. FDL Christoph Hazott, Daniel Große
2025	C	`conf`	ProtoLens: Dynamic Transaction Visualization in Virtual Prototypes. FDL Manfred Schlägl, Jonas Reichhardt, Daniel Große
2025	—	`conf`	Refined Notions of QBF Equivalences. JELIA (2) Peter Pfeiffer, Daniel Große, Martina Seidl
2025	—	`conf`	Surfer - An Extensible Waveform Viewer. CAV (4) Frans Skarman, Lucas Klemmer, Daniel Große, Oscar Gustafsson, Kevin Laeufer
2025	J	`jnl`	Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries. Integr. Christoph Hazott, Florian Stögmüller, Daniel Große
2024	A	`conf`	A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level. DATE Manfred Schlägl, Moritz Stockinger, Daniel Große
2024	C	`conf`	An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs. FDL Lucas Klemmer, Daniel Große
2024	J	`jnl`	Introduction to the Special Issue on Specification and Design Languages (FDL 2021). ACM Trans. Embed. Comput. Syst. Julien Deantoni, Alain Girault, Daniel Große
2024	B	`conf`	Relation Coverage: A New Paradigm for Hardware/Software Testing. ETS Christoph Hazott, Daniel Große
2024	A	`conf`	Single Instruction Isolation for RISC-V Vector Test Failures. ICCAD Manfred Schlägl, Daniel Große
2024	B	`conf`	Towards a Highly Interactive Design-Debug-Verification Cycle. ASPDAC Lucas Klemmer, Daniel Große
2024	A	`conf`	Using Formal Verification Methods for Optimization of Circuits Under External Constraints. DATE Daniel Große, Lucas Klemmer, Dominik Bonora
2024	B	`conf`	Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing. ASPDAC Christoph Hazott, Florian Stögmüller, Daniel Große
2024	J	`jnl`	WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lucas Klemmer, Daniel Große
2023	C	`conf`	Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis. FDL Frans Skarman, Lucas Klemmer, Oscar Gustafsson, Daniel Große
2023	—	`conf`	GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development. ACM Great Lakes Symposium on VLSI Manfred Schlägl, Daniel Große
2023	A	`conf`	Improving Design Understanding of Processors leveraging Datapath Clustering. DATE Katharina Ruep, Daniel Große
2023	J	`jnl`	Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV. CoRR Lucas Klemmer, Daniel Große
2022	—	`conf`	An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle. ISVLSI Lucas Klemmer, Daniel Große
2022	B	`conf`	Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2022	—	`conf`	Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
2022	C	`conf`	Formal Verification of SUBLEQ Microcode implementing the RV32I ISA. FDL Lucas Klemmer, Sonja Gurtner, Daniel Große
2022	A*	`conf`	Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
2022	—	`conf`	RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V. ACM Great Lakes Symposium on VLSI Lucas Klemmer, Manfred Schlägl, Daniel Große
2022	J	`jnl`	RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alireza Mahzoon, Daniel Große, Rolf Drechsler
2022	B	`conf`	SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. ETS Katharina Ruep, Daniel Große
2022	A*	`conf`	Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
2022	—	`conf`	WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging. ASP-DAC Lucas Klemmer, Daniel Große
2022	A*	`conf`	Waveform-based performance analysis of RISC-V processors: late breaking results. DAC Lucas Klemmer, Daniel Große
2021	J	`jnl`	Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
2021	—	`conf`	EPEX: Processor Verification by Equivalent Program Execution. ACM Great Lakes Symposium on VLSI Lucas Klemmer, Daniel Große
2021	C	`conf`	Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
2021	—	`conf`	Mutation-based Compliance Testing for RISC-V. ASP-DAC Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
2021	A	`conf`	System Level Verification of Phase-Locked Loop using Metamorphic Relations. DATE Muhammad Hassan, Daniel Große, Rolf Drechsler
2021	—	`conf`	System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. ASP-DAC Muhammad Hassan, Daniel Große, Rolf Drechsler
2021	J	`jnl`	Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
2021	A	`conf`	Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2021	C	`conf`	XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. ISCAS Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große
2020	—	`conf`	ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks. ISMVL Saman Fröhlich, Lucas Klemmer, Daniel Große, Rolf Drechsler
2020	C	`conf`	Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
2020	A*	`conf`	Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side DAC Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	B	`conf`	Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning. IFM Tim Meywerk, Marcel Walter, Daniel Große, Rolf Drechsler
2020	A*	`conf`	Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. DAC Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	—	`conf`	Early Verification of ISA Extension Specifications using Deep Reinforcement Learning. ACM Great Lakes Symposium on VLSI Niklas Bruns, Daniel Große, Rolf Drechsler
2020	C	`conf`	Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. FDL Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
2020	A	`conf`	Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes DATE Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	J	`jnl`	On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. Microprocess. Microsystems Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, Marcel Walter, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler
2020	J	`jnl`	RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler
2020	B	`conf`	RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. ATVA Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	A	`conf`	Towards Formal Verification of Optimized and Industrial Multipliers. DATE Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
2020	C	`conf`	Towards Generation of a Programmable Power Management Unit at the Electronic System Level. DDECS David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
2020	A	`conf`	Towards Specification and Testing of RISC-V ISA Compliance DATE Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	A*	`conf`	Verification for Field-coupled Nanocomputing Circuits. DAC Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
2020	—	`conf`	Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. ACM Great Lakes Symposium on VLSI Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
2020	—	`conf`	Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. ISoLA (3) Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler
2019	—	`conf`	(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. ARC Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler
2019	—	`ch.`	Approximate Hardware Generation Using Formal Techniques. Approximate Circuits Saman Fröhlich, Daniel Große, Rolf Drechsler
2019	—	`conf`	Automated Analysis of Virtual Prototypes at Electronic System Level. ACM Great Lakes Symposium on VLSI Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
2019	J	`jnl`	Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. Int. J. Softw. Tools Technol. Transf. Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	A	`conf`	Data Flow Testing for SystemC-AMS Timed Data Flow Models. DATE Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	A	`conf`	Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. DATE Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
2019	A*	`conf`	Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. DAC Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	—	`conf`	Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems. ATS Rolf Drechsler, Daniel Große
2019	C	`conf`	Functional Coverage-Driven Characterization of RF Amplifiers. FDL Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
2019	—	`conf`	Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. ISVLSI Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
2019	—	`ed.`	Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017] FDL (Selected Papers) Daniel Große, Sara Vinco, Hiren D. Patel
2019	—	`conf`	Maximizing power state cross coverage in firmware-based power management. ASP-DAC Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	A	`conf`	One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. DATE Saman Fröhlich, Daniel Große, Rolf Drechsler
2019	J	`jnl`	Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is ACM J. Emerg. Technol. Comput. Syst. Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
2019	A*	`conf`	RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC Alireza Mahzoon, Daniel Große, Rolf Drechsler
2019	C	`conf`	SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler
2019	—	`conf`	Scalable design for field-coupled nanocomputing circuits. ASP-DAC Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
2019	J	`jnl`	Security validation of VP-based SoCs using dynamic information flow tracking. it Inf. Technol. Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
2019	C	`conf`	Systematic RISC-V based Firmware Design FDL Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Louis-Ferdinand Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
2019	C	`conf`	Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. DSD Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
2019	A	`conf`	Verifying Instruction Set Simulators using Coverage-guided Fuzzing DATE Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	J	`jnl`	Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	J	`jnl`	fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits. CoRR Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
2018	A	`conf`	An exact method for design exploration of quantum-dot cellular automata. DATE Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
2018	A	`conf`	Approximate hardware generation using symbolic computer algebra employing grobner basis. DATE Saman Fröhlich, Daniel Große, Rolf Drechsler
2018	—	`conf`	Approximation-aware testing for approximate circuits. ASP-DAC Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
2018	J	`jnl`	Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
2018	—	`conf`	Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. ISVLSI Alireza Mahzoon, Daniel Große, Rolf Drechsler
2018	C	`conf`	Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. DSD Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
2018	C	`conf`	Extensible and Configurable RISC-V Based Virtual Prototype. FDL Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2018	C	`conf`	Natural Language Based Power Domain Partitioning. DDECS David Lemma, Daniel Große, Rolf Drechsler
2018	A	`conf`	PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. ICCAD Alireza Mahzoon, Daniel Große, Rolf Drechsler
2018	—	`conf`	Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters NORCAS David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
2018	A	`conf`	Resilience evaluation via symbolic fault injection on intermediate code. DATE Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
2018	—	`conf`	SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
2018	A	`conf`	Testbench qualification for SystemC-AMS timed data flow models. DATE Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
2018	—	`conf`	Towards Automated Refinement of TLM Properties to RTL. MBMV Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2018	—	`conf`	Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. ISVLSI Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
2018	C	`conf`	Towards Reversed Approximate Hardware Design. DSD Saman Fröhlich, Daniel Große, Rolf Drechsler
2018	A	`conf`	Towards fully automated TLM-to-RTL property refinement. DATE Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	A	`conf`	An adaptive prioritized GECCO Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2017	A	`conf`	Data flow testing for virtual prototypes. DATE Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
2017	A	`conf`	Early SoC security validation by VP-based static information flow analysis. ICCAD Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	—	`conf`	Error Bounded Exact BDD Minimization in Approximate Computing. ISMVL Saman Fröhlich, Daniel Große, Rolf Drechsler
2017	—	`conf`	Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. MBMV Saman Fröhlich, Daniel Große, Rolf Drechsler
2017	—	`ed.`	Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017. MBMV Daniel Große, Rolf Drechsler
2017	—	`conf`	ProACt: A Processor for High Performance On-demand Approximate Computing. ACM Great Lakes Symposium on VLSI Arun Chandrasekharan, Daniel Große, Rolf Drechsler
2017	—	`conf`	Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction. FORMATS Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
2017	—	`conf`	Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. FDL (Selected Papers) Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	C	`conf`	Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. FDL Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	—	`conf`	Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. ASP-DAC Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
2017	C	`conf`	Yise - a novel framework for boolean networks using y-inverter graphs. MEMOCODE Arun Chandrasekharan, Daniel Große, Rolf Drechsler
2017	J	`jnl`	metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
2016	—	`conf`	Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	A	`conf`	Approximation-aware rewriting of AIGs for error tolerant applications. ICCAD Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	—	`conf`	BDD minimization for approximate computing. ASP-DAC Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
2016	A	`conf`	Compiled symbolic simulation for systemC. ICCAD Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016	B	`conf`	Equivalence checking using Gröbner bases. FMCAD Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
2016	A	`conf`	Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
2016	C	`conf`	Guided lightweight Software test qualification for IP integration using Virtual Prototypes. ICCD Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
2016	C	`conf`	On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. FDL Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016	—	`conf`	ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. CAV (2) Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler
2016	A*	`conf`	Precise error determination of approximated components in sequential circuits with model checking. DAC Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	A	`conf`	Quantitative timing analysis of UML activity diagrams using statistical model checking. DATE Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
2016	—	`conf`	Symbolic Error Metric Determination for Approximate Computing. MBMV Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
2016	A	`conf`	Towards formal verification of real-world SystemC TLM peripheral models - a case study. DATE Hoang Minh Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
2015	B	`conf`	Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. ATVA Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler
2015	—	`conf`	Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. ISVLSI Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
2014	—	`conf`	Constraint-based platform variants specification for early system verification. ASP-DAC Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolfgang Rosenstiel
2014	—	`conf`	Funktionale Abdeckungsanalyse von C-Programmen. MBMV Aljoscha Windhorst, Hoang Minh Le, Daniel Große, Rolf Drechsler
2013	J	`jnl`	Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. Daniel Große, Görschwin Fey, Rolf Drechsler
2013	C	`conf`	Minimal Stimuli Generation in Simulation-Based Verification. DSD Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
2013	A	`conf`	Scalable fault localization for SystemC TLM designs. DATE Hoang Minh Le, Daniel Große, Rolf Drechsler
2013	—	`conf`	Towards automatic scenario generation from coverage information. AST@ICSE Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
2013	A*	`conf`	Verifying SystemC using an intermediate verification language and symbolic simulation. DAC Hoang Minh Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
2012	A	`conf`	A guiding coverage metric for formal verification. DATE Finn Haedicke, Daniel Große, Rolf Drechsler
2012	J	`jnl`	Automatic TLM Fault Localization for SystemC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hoang Minh Le, Daniel Große, Rolf Drechsler
2012	—	`conf`	Behavior Driven Development for circuit design and verification. HLDVT Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
2012	—	`conf`	CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC. MBMV Finn Haedicke, Hoang Minh Le, Daniel Große, Rolf Drechsler
2012	—	`conf`	CRAVE: An advanced constrained random verification environment for SystemC. ISSoC Finn Haedicke, Hoang Minh Le, Daniel Große, Rolf Drechsler
2012	B	`conf`	Completeness-Driven Development. ICGT Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille
2012	C	`conf`	Coverage-Driven Stimuli Generation. DSD Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
2012	J	`jnl`	Equivalence Checking of Reversible Circuits. J. Multiple Valued Log. Soft Comput. Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2012	—	`conf`	From Requirements and Scenarios to ESL Design in SystemC. ISED Hoang M. Le, Daniel Große, Rolf Drechsler
2012	C	`conf`	Localizing features of ESL models for design understanding. FDL Marc Michael, Daniel Große, Rolf Drechsler
2012	Misc	`conf`	The system verification methodology for advanced TLM verification. CODES+ISSS Marcio Ferreira da Silva Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
2011	C	`conf`	Analyzing dependability measures at the Electronic System Level. FDL Marc Michael, Daniel Große, Rolf Drechsler
2011	J	`jnl`	Debugging reversible circuits. Integr. Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
2011	—	`conf`	Designing a RISC CPU in Reversible Logic. ISMVL Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
2011	—	`conf`	Designing a RISC CPU in Reversible Logic. MBMV Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
2011	—	`conf`	Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
2011	—	`conf`	Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
2011	C	`conf`	TLM protocol compliance checking at the Electronic System Level. DDECS Mohamed Bawadekji, Daniel Große, Rolf Drechsler
2011	—	`conf`	Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. ISORC Workshops Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
2011	—	`conf`	metaSMT: Focus on Your Application not on Solver Integration. DIFTS@FMCAD Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
2010	—	`conf`	Automatic Fault Localization for SystemC TLM Designs. MTV Hoang Minh Le, Daniel Große, Rolf Drechsler
2010	C	`conf`	Proving transaction and system-level properties of untimed SystemC TLM designs. MEMOCODE Daniel Große, Hoang Minh Le, Rolf Drechsler
2010	—	`book`	Quality-Driven SystemC Design Daniel Große, Rolf Drechsler
2010	J	`jnl`	Towards Fully Automatic Synthesis of Embedded Software. IEEE Embed. Syst. Lett. Ulrich Kühne, Daniel Große, Rolf Drechsler
2010	—	`conf`	Towards analyzing functional coverage in SystemC TLM property checking. HLDVT Hoang Minh Le, Daniel Große, Rolf Drechsler
2009	—	`conf`	Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
2009	A	`conf`	Debugging of Toffoli networks. DATE Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
2009	—	`conf`	Equivalence Checking of Reversible Circuits. ISMVL Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2009	—	`conf`	Equivalence Checking of Reversible Circuits. MBMV Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2009	J	`jnl`	Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	J	`jnl`	Exact Synthesis of Elementary Quantum Gate Circuits. J. Multiple Valued Log. Soft Comput. Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	—	`conf`	Formal Verification of Abstract SystemC Models. Algorithms and Applications for Next Generation SAT Solvers Daniel Große, Hoang Minh Le, Rolf Drechsler
2009	—	`conf`	Induction-Based Formal Verification of SystemC TLM Designs. MTV Daniel Große, Hoang Minh Le, Rolf Drechsler
2009	A	`conf`	Property analysis and design understanding. DATE Ulrich Kühne, Daniel Große, Rolf Drechsler
2009	Misc	`conf`	Reversible Logic Synthesis with Output Permutation. VLSI Design Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
2009	C	`conf`	SMT-based stimuli generation in the SystemC Verification library. FDL Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
2009	C	`conf`	WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
2008	J	`jnl`	Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Große, Ulrich Kühne, Rolf Drechsler
2008	C	`conf`	Contradiction Analysis for Constraint-based Random Simulation. FDL Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
2008	—	`conf`	Debugging Contradictory Constraints in Constraint-Based Random Simulation. FDL (Selected Papers) Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
2008	—	`conf`	Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2008	—	`conf`	Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV Ulrich Kühne, Daniel Große, Rolf Drechsler
2008	—	`ch.`	Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme [Quality-Driven Design and Verification Flow for Digital Systems]. Ausgezeichnete Informatikdissertationen Daniel Große
2008	A	`conf`	Quantified Synthesis of Reversible Logic. DATE Robert Wille, Hoang Minh Le, Gerhard W. Dueck, Daniel Große
2008	—	`conf`	RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
2008	—	`conf`	Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
2008	—	`conf`	Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
2007	A	`conf`	Estimating functional coverage in bounded model checking. DATE Daniel Große, Ulrich Kühne, Rolf Drechsler
2007	—	`conf`	Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
2007	—	`conf`	Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
2007	A	`conf`	Fast exact Toffoli network synthesis of reversible logic. ICCAD Robert Wille, Daniel Große
2007	—	`conf`	Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
2007	—	`conf`	Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI Daniel Große, Rüdiger Ebendt, Rolf Drechsler
2007	—	`conf`	Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI Ulrich Kühne, Daniel Große, Rolf Drechsler
2007	C	`conf`	Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
2007	—	`conf`	SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2007	C	`conf`	SWORD: A SAT like prover using word level information. VLSI-SoC Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2006	A	`conf`	Avoiding false negatives in formal verification for protocol-driven blocks. DATE Görschwin Fey, Daniel Große, Rolf Drechsler
2006	—	`conf`	HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI Daniel Große, Ulrich Kühne, Rolf Drechsler
2005	—	`conf`	Acceleration of SAT-Based Iterative Property Checking. CHARME Daniel Große, Rolf Drechsler
2005	—	`conf`	CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) Daniel Große, Rolf Drechsler
2005	—	`conf`	Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) Daniel Große, Ulrich Kühne, Rolf Drechsler
2005	—	`conf`	HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV Daniel Große, Ulrich Kühne, Rolf Drechsler
2005	C	`conf`	SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
2004	C	`conf`	Checkers for SystemC designs. MEMOCODE Daniel Große, Rolf Drechsler
2003	—	`conf`	BDD-based verification of scalable designs. HLDVT Daniel Große, Rolf Drechsler
2003	C	`conf`	Efficient Automatic Visualization of SystemC Designs. FDL Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst
2003	J	`jnl`	Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it Inf. Technol. Daniel Große, Rolf Drechsler
2003	—	`conf`	Formal verification of LTL formulas for SystemC designs. ISCAS (5) Daniel Große, Rolf Drechsler
2003	—	`conf`	Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen. MBMV Daniel Große, Rolf Drechsler
2003	—	`conf`	Modeling Multi-Valued Circuits in SystemC. ISMVL Daniel Große, Görschwin Fey, Rolf Drechsler
2002	J	`jnl`	Heuristic Learning Based on Genetic Programming. Genet. Program. Evolvable Mach. Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler
2002	C	`conf`	Reachability Analysis for Formal Verification of SystemC. DSD Rolf Drechsler, Daniel Große
2001	B	`conf`	Heuristic Learning Based on Genetic Programming. EuroGP Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler
2001	—	`conf`	Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker