Daniel G. Saab

78 papers A* 5A 19B 5C 7Misc 7Journal 19Unranked 16

Year	Rank	Type	Title / Venue / Authors
2018	C	`conf`	ESIFT: Efficient System for Error Injection. IOLTS Ninghan Tian, Daniel G. Saab, Jacob A. Abraham
2017	—	`conf`	Automatic Assertion Generation for Simulation, Formal Verification and Emulation. ISVLSI Tong Zhang, Daniel G. Saab, Jacob A. Abraham
2016	—	`conf`	Single Trojan injection model generation and detection. LATS Harini Bhamidipati, Daniel G. Saab, Jacob A. Abraham
2015	A	`conf`	Formal Verification ATPG Search Engine Emulator (Abstract Only). FPGA Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab
2012	A	`conf`	Ultra-low power NEMS FPGA. ICCAD Sijing Han, Vijay Sirigiri, Daniel G. Saab, Massood Tabib-Azar
2011	—	`conf`	Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling. ISQED Khawla Alzoubi, Daniel G. Saab, Sijing Han, Massood Tabib-Azar
2010	B	`conf`	Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA. FPL Vijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, Massood Tabib-Azar
2009	—	`conf`	Complementary nano-electromechanical switches for ultra-low power embedded processors. ACM Great Lakes Symposium on VLSI Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar
2009	J	`jnl`	Exact Path Delay Fault Coverage Calculation of Partitioned Circuits. IEEE Trans. Computers Fatih Kocan, Lun Li, Daniel G. Saab
2007	B	`conf`	Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. ETS Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab
2007	—	`conf`	Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. ERSA Jason Meyer, Fatih Kocan, Daniel G. Saab
2007	J	`jnl`	Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. J. Electron. Test. Fatih Kocan, Daniel G. Saab
2007	—	`conf`	Reducing verification overhead with RTL slicing. ACM Great Lakes Symposium on VLSI Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham
2007	Misc	`conf`	Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. VLSI Design Jacob A. Abraham, Daniel G. Saab
2007	—	`conf`	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ASP-DAC Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab
2006	Misc	`conf`	Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. VLSI Design Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
2006	A	`conf`	HDL Program Slicing to Reduce Bounded Model Checking Search Overhead. ITC Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham
2005	B	`conf`	An Emulation Model for Sequential ATPG-Based Bounded Model Checking. FPL Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
2005	C	`conf`	Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. ICCD Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham
2003	Misc	`conf`	Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. VLSI Design Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula
2002	J	`jnl`	Correction to "ATPG for combinational circuits on configurable hardware". IEEE Trans. Very Large Scale Integr. Syst. Fatih Kocan, Daniel G. Saab
2002	B	`conf`	Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. FPL Daniel G. Saab, Fatih Kocan, Jacob A. Abraham
2002	A	`conf`	Verifying Properties Using Sequential ATPG. ITC Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
2001	J	`jnl`	ATPG for combinational circuits on configurable hardware. IEEE Trans. Very Large Scale Integr. Syst. Fatih Kocan, Daniel G. Saab
2000	Misc	`conf`	Hierarchical Test Generation for Systems On a Chip. VLSI Design Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab
2000	—	`conf`	Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA. CICC Tarachand Pagarani, Fatih Kocan, Daniel G. Saab, Jacob A. Abraham
1999	A*	`conf`	A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. DAC Miron Abramovici, José T. de Sousa, Daniel G. Saab
1999	J	`jnl`	Combining multiple DFT schemes with test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ben Mathew, Daniel G. Saab
1999	A	`conf`	Concurrent D-algorithm on reconfigurable hardware. ICCAD Fatih Kocan, Daniel G. Saab
1999	A*	`conf`	Dynamic Fault Diagnosis on Reconfigurable Hardware. DAC Fatih Kocan, Daniel G. Saab
1998	C	`conf`	Dynamic fault diagnosis for sequential circuits on reconfigurable hardware. ICCD Fatih Kocan, Daniel G. Saab
1998	J	`jnl`	Initialization of Sequential Circuits and its Application to ATPG. J. Electron. Test. Jalal A. Wehbeh, Daniel G. Saab
1997	B	`conf`	Satisfiability on reconfigurable hardware. FPL Miron Abramovici, Daniel G. Saab
1996	J	`jnl`	Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
1996	Misc	`conf`	Initialization of sequential circuits and its application to ATPG. VTS Jalal A. Wehbeh, Daniel G. Saab
1996	J	`jnl`	Site Partitioning for Redundant Arrays of Distributed Disks. J. Parallel Distributed Comput. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
1995	A	`conf`	DFT & ATPG: Together Again. ITC Ben Mathew, Daniel G. Saab
1994	—	`conf`	Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel
1994	—	`conf`	Efficient simulation of switch-level circuits in a hierarchical simulation environment. Great Lakes Symposium on VLSI Jalal A. Wehbeh, Daniel G. Saab
1994	A	`conf`	Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. ICCAD Daniel G. Saab, Youssef Saab, Jacob A. Abraham
1994	A	`conf`	On the Initialization of Sequential Circuits. ITC Jalal A. Wehbeh, Daniel G. Saab
1994	J	`jnl`	Partial Reset: An Alternative DFT Approach. VLSI Design Ben Mathew, Daniel G. Saab
1994	J	`jnl`	Structural and behavioral synthesis for testability techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab
1993	J	`jnl`	A novel behavioral testability measure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Hsing Chen, Daniel G. Saab
1993	—	`conf`	Assigning Sites fto Redundant Clusters in a Distributed Storage System. ICPP (1) Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
1993	A	`conf`	Augmented partial reset. ICCAD Ben Mathew, Daniel G. Saab
1993	J	`jnl`	Benchmarking Parallel Processing Platforms: An Applications Perspective. IEEE Trans. Parallel Distributed Syst. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
1993	A	`conf`	CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. ITC Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab
1993	J	`jnl`	Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits. Simul. Robert B. Mueller-Thuns, Joseph T. Rahmeh, Jacob A. Abraham, Jalal A. Wehbeh, Daniel G. Saab
1993	A	`conf`	Fault behavior dictionary for simulation of device-level transients. ICCAD Gwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab
1993	A	`conf`	On Selecting Flip-Flops for Partial Reset. ITC Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab
1993	J	`jnl`	Parallel-concurrent fault simulation. IEEE Trans. Very Large Scale Integr. Syst. Daniel G. Saab
1993	—	`conf`	Performance of Redundant Disk Array Organizations in Transaction Processing Environments. ICPP (1) Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
1993	J	`jnl`	Recovery Issues in Databases Using Redundant Disk Arrays. J. Parallel Distributed Comput. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
1993	J	`jnl`	Switch-level timing simulation of bipolar ECL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj
1993	J	`jnl`	VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
1992	A	`conf`	Behavioral synthesis for testability. ICCAD Chung-Hsing Chen, Daniel G. Saab
1992	A	`conf`	CRIS: a test cultivation program for sequential VLSI circuits. ICCAD Daniel G. Saab, Youssef Saab, Jacob A. Abraham
1992	A*	`conf`	Database Recovery Using Redundant Disk Arrays. ICDE Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
1992	C	`conf`	Hierarchical Simulation of MOS Circuits Using Extracted Functional Models. ICCD Jalal A. Wehbeh, Daniel G. Saab
1992	Misc	`conf`	Robust switch-level test generation. VTS Ben Mathew, Daniel G. Saab
1992	—	`conf`	Site Partitioning for Distributed Redundant Disk Arrays. RIDE-TQP Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
1991	C	`conf`	Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability. ICCD Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab
1991	A	`conf`	BETA: Behavioral Testability Analysis. ICCAD Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab
1991	Misc	`conf`	Fault modeling and testing of self-timed circuits. VTS Stanford S. Guillory, Daniel G. Saab, Andrew T. Yang
1991	—	`conf`	Functional abstraction of logic gates for switch-level simulation. EURO-DAC David T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
1991	—	`conf`	Parallel switch-level simulation for VLSI. EURO-DAC Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham
1990	—	`conf`	Derivation of signal flow for switch-level simulation. EURO-DAC David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham
1990	A	`conf`	Design of a scalable parallel switch-level simulator for VLSI. SC Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham
1990	C	`conf`	Fault grading of large digital systems. ICCD Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham
1990	J	`jnl`	Hierarchical multi-level fault simulation of large systems. J. Electron. Test. Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham
1990	A	`conf`	SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
1989	A*	`conf`	Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
1989	C	`conf`	Parallel-concurrent fault simulation. ICCD Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh
1989	A	`conf`	Portable parallel logic and fault simulation. ICCAD Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
1988	A	`conf`	CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. ICCAD Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh
1988	A*	`conf`	Delay Modeling and Time of Bipolar Digital Circuits. DAC Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj
1987	J	`jnl`	Switch-Level Logic Simulation of Digital Bipolar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ibrahim N. Hajj, Daniel G. Saab