Daniel Eckerbert

13 papers C 3Journal 3Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Wideband Sub-6-GHz Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS. IEEE J. Solid State Circuits Christian Elgaard, Mohammed Abdulaziz, Tony Påhlsson, Bengt Edholm, Florent Torres, Fabien Mesquita, Martin Hansson, Daniel Eckerbert, Stefan Back Andersson, Sven Mattisson, Henrik Sjöland
2013	—	`conf`	A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. ISSCC Lars Sundström, Martin Anderson, Roland Strandberg, Staffan Ek, Jim Svensson, Fenghao Mu, Thomas Olsson, Imad ud Din, Leif R. Wilhelmsson, Daniel Eckerbert, Sven Mattisson
2013	J	`jnl`	Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. IEEE J. Solid State Circuits Lars Sundström, Staffan Ek, Jim Svensson, Martin Anderson, Roland Strandberg, Fenghao Mu, Imad ud Din, Thomas Olsson, Leif R. Wilhelmsson, Daniel Eckerbert
2012	—	`conf`	A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. ESSCIRC Martin Anderson, Roland Strandberg, Staffan Ek, Leif R. Wilhelmsson, Lars Sundström, Mattias Andersson, Imad ud Din, Jim Svensson, Thomas Olsson, Daniel Eckerbert
2012	—	`conf`	Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS. ESSCIRC Lars Sundström, Staffan Ek, Jim Svensson, Martin Anderson, Roland Strandberg, Fenghao Mu, Imad ud Din, Thomas Olsson, Leif R. Wilhelmsson, Daniel Eckerbert
2006	J	`jnl`	Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. Very Large Scale Integr. Syst. Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
2004	—	`conf`	A power cut-off technique for gate leakage suppression [CMOS logic circuits]. ESSCIRC Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson
2003	C	`conf`	A Mixed-Mode Delay-Locked-Loop Architecture. ICCD Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors
2003	—	`conf`	A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. ASP-DAC Daniel Eckerbert, Per Larsson-Edefors
2003	—	`conf`	Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson
2001	—	`conf`	Cycle-true leakage current modeling for CMOS gates. ISCAS (5) Daniel Eckerbert, Per Larsson-Edefors
2001	C	`conf`	Interconnect-Driven Short-Circuit Power Modeling. DSD Daniel Eckerbert, Per Larsson-Edefors
2000	C	`conf`	An interconnect-driven design of a DFT processor. ISCAS Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman