Daniel D. Gajski

96 papers A* 6A 5B 3C 8Misc 3Journal 29Unranked 39

Year	Rank	Type	Title / Venue / Authors
2014	—	`conf`	Hierarchy-Aware mapping of pipelined applications. MWSCAS Kyoungwon Kim, Daniel D. Gajski
2014	—	`conf`	Trace-Driven Performance Estimation of multi-core platforms. MWSCAS Kyoungwon Kim, Daniel D. Gajski
2012	J	`jnl`	Automated Generation of Custom Processor Core from C Code. J. Electr. Comput. Eng. Jelena Trajkovic, Samar Abdi, Gabriela Nicolescu, Daniel D. Gajski
2011	J	`jnl`	Automatic TLM Generation for Early Validation of Multicore Systems. IEEE Des. Test Comput. Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski
2010	A	`conf`	Accurate timed RTOS model for transaction level modeling. DATE Yonghyun Hwang, Gunar Schirner, Samar Abdi, Daniel D. Gajski
2010	—	`conf`	Early performance-cost estimation of application-specific data path pipelining. SASP Jelena Trajkovic, Daniel D. Gajski
2010	C	`conf`	Embedded system environment: A framework for TLM-based design and prototyping. International Symposium on Rapid System Prototyping Samar Abdi, Yonghyun Hwang, Lochi Yu, Hansu Cho, Ines Viskic, Daniel D. Gajski
2009	J	`jnl`	An Introduction to High-Level Synthesis. IEEE Des. Test Comput. Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach
2009	J	`jnl`	Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, Jürgen Teich
2008	—	`conf`	Custom Processor Core Construction from C Code. SASP Jelena Trajkovic, Daniel D. Gajski
2008	—	`conf`	Model Based Synthesis of Embedded Software. SEUS Daniel D. Gajski, Samar Abdi, Ines Viskic
2008	J	`jnl`	System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Embed. Syst. Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski
2007	—	`conf`	An Interactive Design Environment for C-based High-Level Synthesis. IESS Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
2007	B	`conf`	Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. LCTES Ines Viskic, Samar Abdi, Daniel D. Gajski
2007	C	`conf`	New Strategies for System-Level Design. DDECS Daniel D. Gajski
2007	A*	`conf`	TLM: Crossing Over From Buzz To Adoption. DAC Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil
2006	Misc	`conf`	Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski
2006	—	`conf`	Designing a custom architecture for DCT using NISC technology. ASP-DAC Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski
2005	—	`conf`	Automatic Generation of Communication Architectures. IESS Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
2005	Misc	`conf`	Automatic network generation for system-on-chip communication design. CODES+ISSS Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
2005	—	`conf`	Custom Processor Design Using NISC: A Case-Study on DCT algorithm. ESTIMedia Bita Gorjiara, Daniel D. Gajski
2005	A	`conf`	Defining an Enhanced RTL Semantics. DATE Shuqing Zhao, Daniel D. Gajski
2005	A	`conf`	Functional Validation of System Level Static Scheduling. DATE Samar Abdi, Daniel D. Gajski
2005	—	`conf`	Software and Driver Synthesis from Transaction Level Models. IESS Haobo Yu, Rainer Dömer, Daniel D. Gajski
2005	C	`conf`	Structural operational semantics for supporting multi-cycle operations in RTL HDLs. MEMOCODE Shuqing Zhao, Daniel D. Gajski
2005	—	`conf`	System-level communication modeling for network-on-chip synthesis. ASP-DAC Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski
2005	C	`conf`	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. ICCD Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski
2003	—	`ch.`	RTOS Modeling for System Level Design. Embedded Software for SoC Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski
2002	J	`jnl`	An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. Jianwen Zhu, Daniel D. Gajski
2002	—	`conf`	Co-design of embedded controllers for power electronics and electric systems. ISIC Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer
2002	B	`conf`	Seamless approach for the design of control systems for power electronics and electric drives. SMC Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer
2001	—	`book`	System Design - A Practical Guide with SpecC. Andreas Gerstlauer, Rainer Dömer, Junyu Peng, Daniel D. Gajski
1999	J	`jnl`	Partitioning and pipelining for performance-constrained hardware/software systems. IEEE Trans. Very Large Scale Integr. Syst. Smita Bakshi, Daniel D. Gajski
1998	C	`conf`	Hierarchical pipelining for behaviors, loops, and operations. ICCD Smita Bakshi, Daniel D. Gajski
1998	J	`jnl`	SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. Very Large Scale Integr. Syst. Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
1998	J	`jnl`	Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. Rainer Dömer, Daniel D. Gajski, Jianwen Zhu
1997	—	`conf`	A quantitative analysis for optimizing memory allocation. ASP-DAC Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski
1996	—	`conf`	Clock optimization for high-performance pipelined design. EURO-DAC Hsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski
1996	J	`jnl`	Component selection for high-performance pipelines. IEEE Trans. Very Large Scale Integr. Syst. Smita Bakshi, Daniel D. Gajski
1996	—	`conf`	Component selection in resource shared and pipelined DSP applications. EURO-DAC Smita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan
1996	—	`conf`	Model Refinement for Hardware-Software Codesign. ED&TC Jie Gong, Daniel D. Gajski, Smita Bakshi
1996	—	`conf`	Rapid performance estimation for system design. EURO-DAC Sanjiv Narayan, Daniel D. Gajski
1996	J	`jnl`	System design methodologies: aiming at the 100 h design cycle. IEEE Trans. Very Large Scale Integr. Syst. Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung
1995	—	`conf`	A memory selection algorithm for high-performance pipelines. EURO-DAC Smita Bakshi, Daniel D. Gajski
1995	—	`conf`	Architectural exploration for datapaths with memory hierarchy. ED&TC Nancy D. Holmes, Daniel D. Gajski
1995	—	`conf`	Closeness metrics for system-level functional partitioning. EURO-DAC Frank Vahid, Daniel D. Gajski
1995	—	`conf`	Clustering for improved system-level functional partitioning. ISSS Frank Vahid, Daniel D. Gajski
1995	J	`jnl`	Incremental hardware estimation during hardware/software functional partitioning. IEEE Trans. Very Large Scale Integr. Syst. Frank Vahid, Daniel D. Gajski
1995	J	`jnl`	Performance evaluation for application-specific architectures. IEEE Trans. Very Large Scale Integr. Syst. Jie Gong, Daniel D. Gajski, Alexandru Nicolau
1995	—	`conf`	SLIF: a specification-level intermediate format for system design. ED&TC Frank Vahid, Daniel D. Gajski
1995	—	`conf`	Software estimation using a generic-processor model. ED&TC Jie Gong, Daniel D. Gajski, Sanjiv Narayan
1995	J	`jnl`	SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
1995	J	`jnl`	Specification and Design of Embedded Hardware-Software Systems. IEEE Des. Test Comput. Daniel D. Gajski, Frank Vahid
1994	—	`conf`	100-hour design cycle: a test case. EURO-DAC Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung
1994	—	`conf`	A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. EURO-DAC Frank Vahid, Daniel D. Gajski, Jie Gong
1994	—	`conf`	A component selection algorithm for high-performance pipelines. EURO-DAC Smita Bakshi, Daniel D. Gajski
1994	—	`conf`	A performance evaluator for parameterized ASIC architectures. EURO-DAC Jie Gong, Daniel D. Gajski, Alex Nicolau
1994	—	`conf`	A transformation for integrating VHDL behavioral specification with synthesis and software generation. EURO-DAC Frank Vahid, Daniel D. Gajski, Sanjiv Narayan
1994	J	`jnl`	A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
1994	A	`conf`	Condition graphs for high-quality behavioral synthesis. ICCAD Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski
1994	A	`conf`	Design exploration for high-performance pipelines. ICCAD Smita Bakshi, Daniel D. Gajski
1994	J	`jnl`	Introduction to High-Level Synthesis. IEEE Des. Test Comput. Daniel D. Gajski, Loganath Ramachandran
1993	—	`conf`	Architectural tradeoffs in synthesis of pipelined controls. EURO-DAC Loganath Ramachandran, Daniel D. Gajski
1993	J	`jnl`	Component synthesis from functional descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elke A. Rundensteiner, Daniel D. Gajski, Lubomir Bic
1993	—	`conf`	Features supporting system-level specification in HDLs. EURO-DAC Sanjiv Narayan, Daniel D. Gajski
1993	—	`conf`	Synthesis of functions and procedures in behavioral VHDL. EURO-DAC Loganath Ramachandran, Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
1993	—	`conf`	Top-down modeling of RISC processors in VHDL. EURO-DAC Hsiao-Ping Juan, Nancy D. Holmes, Smita Bakshi, Daniel D. Gajski
1992	J	`jnl`	Layout placement for sliced architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu
1992	J	`jnl`	Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Allen C.-H. Wu, Daniel D. Gajski
1992	—	`conf`	Semantics and synthesis of signals in behavioral VHDL. EURO-DAC Loganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
1992	Misc	`conf`	System Level Specification and Synthesis. VLSI Design Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
1992	J	`jnl`	System Specification with the SpecCharts Language. IEEE Des. Test Comput. Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
1992	—	`conf`	System clock estimation based on clock slack minimization. EURO-DAC Sanjiv Narayan, Daniel D. Gajski
1992	—	`conf`	Timing models for high-level synthesis. EURO-DAC Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski
1992	—	`book`	Youn-Long Steve Lin Daniel D. Gajski, Nikil D. Dutt, Allen C.-H. Wu
1991	—	`conf`	Glue-logic partitioning for floorplans with a rectilinear datapath. EURO-DAC Allen C.-H. Wu, Daniel D. Gajski
1991	—	`conf`	Translating system specifications to VHDL. EURO-DAC Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
1990	J	`jnl`	Chippe: a system for constraint driven behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Forrest Brewer, Daniel D. Gajski
1990	J	`jnl`	Design Synthesis and Silicon Compilation. IEEE Des. Test Comput. Nikil D. Dutt, Daniel D. Gajski
1990	J	`jnl`	The Role of Learning in Logic Synthesis. Int. J. Pattern Recognit. Artif. Intell. James R. Kipps, Daniel D. Gajski
1989	J	`jnl`	Computer-aided programming for message-passing systems: problems and solutions. Proc. IEEE Min-You Wu, Daniel D. Gajski
1989	—	`conf`	The role of learning in logic synthesis. TAI James R. Kipps, Daniel D. Gajski
1988	J	`jnl`	A programming aid for hypercube architectures. J. Supercomput. Min-You Wu, Daniel D. Gajski
1988	J	`jnl`	A technique for pull-up transistor folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chidchanok Lursinsap, Daniel D. Gajski
1988	J	`jnl`	LES: a layout expert system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youn-Long Lin, Daniel D. Gajski
1988	C	`conf`	Synthesis from VHDL. ICCD Joseph Lis, Daniel D. Gajski
1987	J	`jnl`	Design Tools for Intelligent Silicon Compilation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Barry M. Pangrle, Daniel D. Gajski
1985	C	`ed.`	7th IEEE Symposium on Computer Arithmetic, ARITH 1985, Urbana, IL, USA, June 4-6, 1985 IEEE Symposium on Computer Arithmetic Daniel D. Gajski, Ahmed H. Sameh, Kai Hwang
1985	A*	`conf`	Decomposition of logic networks into silicon. DAC Steven T. Healey, Daniel D. Gajski
1984	—	`conf`	Cedar. COMPCON Daniel D. Gajski, Duncan H. Lawrie, David J. Kuck, Ahmed H. Sameh
1984	A*	`conf`	Microprocessor synthesis. DAC Vijay K. Raj, Barry M. Pangrle, Daniel D. Gajski
1984	A*	`conf`	Silicon compilers and expert systems for VLSI. DAC Daniel D. Gajski
1982	B	`conf`	Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor. ICPP Daniel D. Gajski, Ahmed H. Sameh, John A. Wisniewski
1981	A*	`conf`	Automatic generation of cells for recurrence structures. DAC Avinoam Bilgory, Daniel D. Gajski
1980	A*	`conf`	Automatic design with dependence graphs. DAC Albert E. Casavant, Daniel D. Gajski, David J. Kuck
1978	C	`conf`	Design of arithmetic elements for Burroughs Scientific Processor. IEEE Symposium on Computer Arithmetic Daniel D. Gajski, Louis P. Rubinfield