Daniel Chillet

84 papers A* 2A 3B 4C 8Misc 3Journal 19Unranked 36

Year	Rank	Type	Title / Venue / Authors
2026	—	`ed.`	Proceedings of the Rapid Simulation and Performance Evaluation for Design, RAPIDO 2026, Kraków, Poland, 27 January 2026 RAPIDO@HiPEAC Lilia Zaourar, Morteza Biglari-Abhari, Daniel Chillet, Daniel Gracia Pérez, Réda Nouacer, Matthias Jung, Gianluca Palermo
2026	—	`conf`	Selective Triplication for Fault-Tolerant Systolic Array Processing Elements. RAPIDO@HiPEAC Wilfread Guillemé, Gaëtan Lounes, Angeliki Kritikakou, Youri Helen, Robin Gerzaguet, Matthieu Gautier, Cédric Killian, Daniel Chillet
2025	—	`conf`	DyEKF: Dynamic Protection of Approximate NoC Communications Against Hardware Trojan Attacks. SOCC Hamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau
2025	—	`conf`	Empirical Analysis and Estimation of the Energy Cost of Data Transfers in CPU Caches in Multi-Core Systems. MECO Gaëtan Barret, Joël Penhoat, Roland Picard, Daniel Chillet
2025	C	`conf`	Fault Tolerance in Quantized and Pruned Convolutional Neural Networks. IOLTS Wilfread Guillemé, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet
2025	—	`ed.`	Proceedings of the Rapid Simulation and Performance Evaluation for Design Workshop, RAPIDO 2025, Barcelona, Spain, 21 January 2025 RAPIDO@HiPEAC Lilia Zaourar, Morteza Biglari-Abhari, Daniel Chillet, Daniel Gracia Pérez, Réda Nouacer, Matthias Jung, Gianluca Palermo
2025	—	`conf`	Towards Accurate Static Power Model on Multi-Core Operating Systems. RAPIDO@HiPEAC Gaëtan Barret, Daniel Chillet, Roland Picard, Joël Penhoat
2024	—	`conf`	FPGA-based CNN Acceleration using Pattern-Aware Pruning. AICAS Léo Pradels, Silviu-Ioan Filip, Olivier Sentieys, Daniel Chillet, Thibaut Le Calloch
2024	A*	`conf`	HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks. DAC Wilfread Guillemé, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet
2024	—	`conf`	Mitigation of Hardware Trojan in NoC using Delta-Based Compression. SOCC Hamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau
2024	—	`ed.`	Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, RAPIDO 2024, Munich, Germany, 18 January 2024 RAPIDO@HiPEAC Lilia Zaourar, Daniel Chillet, Daniel Gracia Pérez, Morteza Biglari-Abhari, Réda Nouacer, Matthias Jung, Gianluca Palermo
2024	C	`conf`	VANDOR: Mitigating SEUs into Quantized Neural Networks. IOLTS Wilfread Guillemé, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet
2023	J	`jnl`	Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs. IEEE Des. Test Ibrahim Krayem, Joel Ortiz Sosa, Cédric Killian, Daniel Chillet
2022	J	`jnl`	BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet
2022	—	`conf`	Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing. NANOARCH Ibrahim Krayem, Romain Mercier, Cédric Killian, Angeliki Kritikakou, Daniel Chillet
2022	J	`jnl`	Distance-aware Approximate Nanophotonic Interconnect. ACM Trans. Design Autom. Electr. Syst. Jaechul Lee, Cédric Killian, Sébastien Le Beux, Daniel Chillet
2021	—	`conf`	A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency. DFT Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet
2021	—	`ed.`	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings ARC Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet
2020	J	`jnl`	Energy-Efficient Scheduling of Real-Time Tasks in Reconfigurable Homogeneous Multicore Platforms. IEEE Trans. Syst. Man Cybern. Syst. Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet
2020	C	`conf`	Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture. ICCD Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet
2019	—	`conf`	Approximate nanophotonic interconnects. NOCS Jaechul Lee, Cédric Killian, Sébastien Le Beux, Daniel Chillet
2019	—	`ed.`	Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO 2019, Valencia, Spain, January 21-23, 2019. RAPIDO Daniel Chillet
2018	B	`conf`	Mapping of Periodic Tasks in Reconfigurable Heterogeneous Multi-core Platforms. ENASE Aymen Gammoudi, Daniel Chillet, Mohamed Khalgui, Adel Benzina
2018	J	`jnl`	Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects. ACM J. Emerg. Technol. Comput. Syst. Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Olivier Sentieys, Ian O'Connor
2018	—	`ed.`	Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Manchester, UK, January 22-24, 2018. RAPIDO Daniel Chillet
2018	—	`conf`	Run-Time management of energy-performance trade-off in Optical Network-on-Chip. DCIS Jiating Luo, Van-Dung Pham, Cédric Killian, Daniel Chillet, Ian O'Connor, Olivier Sentieys, Sébastien Le Beux
2017	A*	`conf`	Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. DAC Cédric Killian, Daniel Chillet, Sébastien Le Beux, Van-Dung Pham, Olivier Sentieys, Ian O'Connor
2017	A	`conf`	Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC. DATE Jiating Luo, A. Elantably, Van-Dung Pham, Cédric Killian, Daniel Chillet, Sébastien Le Beux, Olivier Sentieys, Ian O'Connor
2016	J	`jnl`	Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems. J. Low Power Electron. Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys
2016	B	`conf`	Real-Time Scheduling of Reconfigurable Battery-Powered Multi-Core Platforms. ICTAI Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet
2015	—	`conf`	Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip. SiPhotonics@HiPEAC Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys
2015	—	`conf`	Communication Aware Design Method for Optical Network-on-Chip. MCSoC Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cédric Killian, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys
2015	C	`conf`	New Pack Oriented Solutions for Energy-Aware Feasible Adaptive Real-Time Systems. SoMeT Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet
2015	—	`ed.`	Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015, Amsterdam, The Netherlands RAPIDO@HiPEAC Gianluca Palermo, Daniel Gracia Pérez, Morteza Biglari-Abhari, Daniel Chillet, Smaïl Niar, Adam Morawiec
2014	—	`conf`	Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA. AHS Quang-Hai Khuat, Daniel Chillet, Michael Hübner
2014	—	`conf`	Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC. ReConFig Quang-Hai Khuat, Daniel Chillet, Michael Hübner
2014	—	`conf`	Intrinsic Fault Tolerance of Hopfield Artificial Neural Network Model for Task Scheduling Technique in SoC. IJCCI (NCTA) Rajhans Singh, Daniel Chillet
2014	J	`jnl`	Power consumption models for the use of dynamic and partial reconfiguration. Microprocess. Microsystems Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys
2014	—	`ed.`	Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '14, 22 January, 2014, Vienna, Austria RAPIDO Daniel Gracia Pérez, Morteza Biglari-Abhari, Daniel Chillet, Gianluca Palermo
2014	J	`jnl`	Special issue on design and architectures of real-time image processing in embedded systems. J. Real Time Image Process. Daniel Chillet, Michael Hübner
2013	J	`jnl`	An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC. IEEE Trans. Ind. Informatics Rabie Ben Atitallah, Eric Senn, Daniel Chillet, Mickael Lanoe, Dominique Blouin
2013	—	`conf`	Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource. DASIP Quang-Hai Khuat, Daniel Chillet
2013	—	`conf`	Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture. IDT Quang-Hai Khuat, Quang-Hoa Le, Daniel Chillet, Sébastien Pillement
2012	C	`conf`	Open-People: Open Power and Energy Optimization PLatform and Estimator. DSD Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Sébastien Bilavarn, Rabie Ben Atitallah, Christian Samoyeau, A. Fritsch
2012	—	`conf`	Open-people: An open platform for estimation and optimizations of energy consumption. DASIP Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Rabie Ben Atitallah, A. Fritsch, Christian Samoyeau
2012	—	`conf`	Power consumption model for partial and dynamic reconfiguration. ReConFig Robin Bonamy, Daniel Chillet, Sébastien Bilavarn, Olivier Sentieys
2012	—	`ed.`	Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '13, 21 January, 2013, Berlin, Germany RAPIDO Daniel Gracia Pérez, Morteza Biglari-Abhari, Daniel Chillet, Gianluca Palermo
2012	A	`conf`	UPaRC - Ultra-fast power-aware reconfiguration controller. DATE Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet
2011	J	`jnl`	AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. Int. J. Reconfigurable Comput. Dominique Blouin, Daniel Chillet, Eric Senn, Sébastien Bilavarn, Robin Bonamy, Christian Samoyeau
2011	C	`conf`	Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. VLSI-SoC Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis
2011	—	`conf`	Hardware OS Communication Service and Dynamic Memory Management for RSoCs. ReConFig Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis
2011	—	`conf`	Parallel Evaluation of Hopfield Neural Networks. IJCCI (NCTA) Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2011	J	`jnl`	Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. SIGARCH Comput. Archit. News Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sébastien Bilavarn
2011	J	`jnl`	Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. J. Syst. Archit. Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys
2011	—	`conf`	Towards a power and energy efficient use of partial dynamic reconfiguration. ReCoSoC Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sébastien Bilavarn
2010	J	`jnl`	Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny
2010	—	`conf`	Mesh and Fat-Tree comparison for dynamically reconfigurable applications. ReCoSoC Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny
2010	—	`conf`	Open-People: Open Power and Energy Optimization PLatform and Estimator. PATMOS Daniel Chillet
2010	—	`conf`	R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. ReConFig Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny
2010	—	`conf`	Task placement for dynamic and partial reconfigurable architecture. DASIP Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2009	—	`conf`	High-Level Exploration for Dynamic Reconfiguration Management. ERSA Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet
2009	J	`jnl`	OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. Int. J. Reconfigurable Comput. Benoît Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, Thomas LeFebvre, Mehdi Aïchouch, Jean-Christophe Prévotet, Yaset Oliva, Daniel Chillet, Sébastien Pillement
2008	—	`conf`	A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement
2008	J	`jnl`	Structure mémoire reconfigurable. Vers une structure de stockage faible consommation. Tech. Sci. Informatiques Daniel Chillet, Raphaël David, Erwan Grâce, Olivier Sentieys
2007	B	`conf`	A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2007	—	`conf`	Hardware task scheduling for heterogeneous soc architectures. EUSIPCO Imene Benkermi, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2006	J	`jnl`	Floating-to-Fixed-Point Conversion for Digital Signal Processors. EURASIP J. Adv. Signal Process. Daniel Ménard, Daniel Chillet, Olivier Sentieys
2005	—	`conf`	Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys
2005	—	`conf`	Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement
2003	J	`jnl`	Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. Tech. Sci. Informatiques Daniel Ménard, Taofik Saïdi, Daniel Chillet, Olivier Sentieys
2002	B	`conf`	A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2002	Misc	`conf`	Automatic floating-point to fixed-point conversion for DSP code generation. CASES Daniel Ménard, Daniel Chillet, François Charot, Olivier Sentieys
2002	—	`conf`	Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED Sébastien Pillement, Daniel Chillet, Olivier Sentieys
2002	A	`conf`	DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2002	Misc	`conf`	Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture. ICASSP Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2001	C	`conf`	A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
2000	J	`jnl`	A Framework for High Level Estimations of Signal Processing VLSI Implementations. J. VLSI Signal Process. Jean-Philippe Diguet, Daniel Chillet, Olivier Sentieys
2000	C	`conf`	Multi-algorithm ASIP synthesis and power estimation for DSP applications. ISCAS Jean-Gabriel Cousin, Olivier Sentieys, Daniel Chillet
2000	J	`jnl`	Teaching hardware/software system codesign using CAD tools: a case study in image synthesis. IEEE Trans. Educ. Hélène Dubois, Olivier Sentieys, Daniel Chillet, Jean Luc Philippe
1999	—	`conf`	Behavioral synthesis of asynchronous systems: a methodology. ISCAS (6) J. O. Dedou, Daniel Chillet, Olivier Sentieys
1999	—	`conf`	Memory Unit Design for Real Time DSP Applications. Great Lakes Symposium on VLSI Daniel Chillet, Olivier Sentieys, Michel Corazza
1998	—	`conf`	Asynchronous timing model for high-level synthesis of DSP applications. EUSIPCO J. Okito Dedou, Daniel Chillet, Olivier Sentieys
1997	Misc	`conf`	VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters. ICASSP Jean-Philippe Diguet, Olivier Sentieys, Daniel Chillet, Jean Luc Philippe
1996	—	`conf`	Memory aspects in signal processing and HLS tool: Some results. EUSIPCO Jean Luc Philippe, Daniel Chillet, Olivier Sentieys, Jean-Philippe Diguet