Daniel Auvergne

46 papers A 3B 1C 2Journal 13Unranked 27

Year	Rank	Type	Title / Venue / Authors
2007	J	`jnl`	Low Power Oriented CMOS Circuit Optimization Protocol CoRR Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
2006	J	`jnl`	Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2005	A	`conf`	Low Power Oriented CMOS Circuit Optimization Protocol. DATE Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
2004	—	`conf`	Delay bound based CMOS gate sizing technique. ISCAS (5) Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2004	—	`conf`	Design Optimization with Automated Cell Generation. PATMOS A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne
2004	—	`conf`	Performance Metric Based Optimization Protocol. PATMOS Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2004	—	`conf`	Physical Extension of the Logical Effort Model. PATMOS B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2004	—	`conf`	Temperature Dependence in Low Power CMOS UDSM Process. PATMOS B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2003	—	`conf`	CMOS Gate Sizing under Delay Constraint. PATMOS Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2003	—	`conf`	Continuous representation of the performance of a CMOS library. ESSCIRC B. Lasbouygues, Joel Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2003	J	`jnl`	Design Techniques for EEPROMs Embedded in Portable Systems on Chips. IEEE Des. Test Comput. Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne
2003	—	`conf`	Metric Definition for Circuit Speed Optimization. PATMOS Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne
2002	—	`conf`	Crosstalk Measurement Technique for CMOS ICs. PATMOS Fabrice Picot, Philippe Coll, Daniel Auvergne
2002	—	`conf`	Gate speed improvement at minimal power dissipation. APCCAS (2) Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne
2002	—	`conf`	Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS Philippe Maurine, Nadine Azémard, Daniel Auvergne
2002	A	`conf`	Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. DATE Wenceslas Rahajandraibe, Christian Dufaza, Daniel Auvergne, Bruno Cialdella, Bernard Majoux, Vivek Chowdhury
2002	—	`conf`	Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. PATMOS Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, Daniel Auvergne
2002	J	`jnl`	Transition time modeling in deep submicron CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne
2001	—	`conf`	Delay bound determination for timing closure satisfaction. ISCAS (5) Nadine Azémard, M. Aline, Daniel Auvergne
2001	C	`conf`	Feasible Delay Bound Definition. VLSI-SOC Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne
2001	C	`conf`	Gate Sizing for Low Power Design. VLSI-SOC Philippe Maurine, Nadine Azémard, Daniel Auvergne
2001	—	`conf`	Output transition time modeling of CMOS structures. ISCAS (5) Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne
2001	J	`jnl`	POPS: A tool for delay/power performance optimization. J. Syst. Archit. Nadine Azémard, Daniel Auvergne
2000	—	`conf`	Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. MTDT Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne
2000	—	`conf`	Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. PATMOS Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne
2000	—	`conf`	Second Generation Delay Model for Submicron CMOS Process. PATMOS Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne
1999	—	`conf`	A Virtual CMOS Library Approach for East Layout Synthesis. VLSI Fernando Moraes, Michel Robert, Daniel Auvergne
1999	J	`jnl`	A comprehensive delay macro modeling for submicrometer CMOS logics. IEEE J. Solid State Circuits Jean Michel Daga, Daniel Auvergne
1999	—	`conf`	Delay-power performance analysis. ICECS S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne
1999	—	`conf`	RF Interface Design Using Mixed-Mode Methodology. VLSI Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne
1998	J	`jnl`	A novel macromodel for power estimation in CMOS structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. S. Turgis, Daniel Auvergne
1998	A	`conf`	Temperature Effect on Delay for Low Voltage Applications. DATE Jean Michel Daga, E. Ottaviano, Daniel Auvergne
1997	—	`conf`	Internal power modelling and minimization in CMOS inverters. ED&TC S. Turgis, Jean Michel Daga, Josep M. Portal, Daniel Auvergne
1996	J	`jnl`	Delay propagation effect in transistor gates. IEEE J. Solid State Circuits Denis Deschacht, Christophe Dabrin, Daniel Auvergne
1996	—	`conf`	Design and selection of buffers for minimum power-delay product. ED&TC S. Turgis, Nadine Azémard, Daniel Auvergne
1995	—	`conf`	Delay modelling improvement for low voltage applications. EURO-DAC Jean Michel Daga, Michel Robert, Daniel Auvergne
1995	—	`conf`	Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD S. Turgis, Nadine Azémard, Daniel Auvergne
1994	B	`conf`	Influence of Locig Block Layout Architecture on FPGA Performance. FPL Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne
1993	J	`jnl`	Post-layout timing simulation of CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne
1992	—	`conf`	P.SIZE: a sizing aid for optimized designs. EURO-DAC Nadine Azémard, V. Bonzom, Daniel Auvergne
1991	—	`conf`	Formal sizing rules of CMOS circuits. EURO-DAC Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert
1991	J	`jnl`	Synchronous-mode evaluation of delays in CMOS structures. IEEE J. Solid State Circuits Denis Deschacht, Michel Robert, Daniel Auvergne
1991	J	`jnl`	TVA: A timing verifier with analytic temporal modelling. Microprocessing and Microprogramming D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne
1990	J	`jnl`	Input waveform slope effects in CMOS delays. IEEE J. Solid State Circuits Daniel Auvergne, Nadine Azémard, Denis Deschacht, Michel Robert
1990	—	`conf`	Path runner: an accurate and fast timing analyser. EURO-DAC Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne
1985	J	`jnl`	FSPICE: a tool for fault modelling in MOS circuits. Integr. Michel Renovell, Gaston Cambon, Daniel Auvergne