Daniel A. Jiménez

97 papers A* 36A 5B 7C 9Journal 26Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Correct Wrong Path. IEEE Comput. Archit. Lett. Bhargav Reddy Godala, Sankara Prasad Ramesh, Krishnam Tibrewala, Chrysanthos Pepi, Gino Chacon, Svilen Kanev, Gilles A. Pokam, Alberto Ros, Daniel A. Jiménez, Paul V. Gratz, David I. August
2025	—	`conf`	Instruction-Aware Cooperative TLB and Cache Replacement Policies. ASPLOS (1) Dimitrios Chasapis, Georgios Vavouliotis, Daniel A. Jiménez, Marc Casas
2025	A*	`conf`	Light-weight Cache Replacement for Instruction Heavy Workloads. ISCA Saba Mostofi, Setu Gupta, Ahmad Hassani, Krishnam Tibrewala, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez
2025	J	`jnl`	R-Max: A Method for Approximating the Benefit of Ideal Prefetching and Replacement Policy. IEEE Comput. Archit. Lett. Lei Wang, Chia-Hang Lee, Maccoy Merrell, Gino Chacon, Daniel A. Jiménez, Paul V. Gratz
2025	—	`conf`	Skia: Exposing Shadow Branches. ASPLOS (2) Chrysanthos Pepi, Bhargav Reddy Godala, Krishnam Tibrewala, Gino A. Chacon, Paul V. Gratz, Daniel A. Jiménez, Gilles A. Pokam, David I. August
2025	J	`jnl`	Workload Characterization for Branch Predictability. CoRR FNU Vikas, Paul Gratz, Daniel A. Jiménez
2024	A*	`conf`	A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. HPCA Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas
2024	J	`jnl`	A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. CoRR Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas
2024	J	`jnl`	Correct Wrong Path. CoRR Bhargav Reddy Godala, Sankara Prasad Ramesh, Krishnam Tibrewala, Chrysanthos Pepi, Gino Chacon, Svilen Kanev, Gilles A. Pokam, Daniel A. Jiménez, Paul V. Gratz, David I. August
2024	J	`jnl`	Exposing Shadow Branches. CoRR Chrysanthos Pepi, Bhargav Reddy Godala, Krishnam Tibrewala, Gino Chacon, Paul V. Gratz, Daniel A. Jiménez, Gilles A. Pokam, David I. August
2024	A*	`conf`	Message from the MICRO 2024 Program Chairs. MICRO Daniel A. Jiménez, Alaa R. Alameldeen
2024	A	`conf`	Practically Tackling Memory Bottlenecks of Graph-Processing Workloads. IPDPS Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas
2023	B	`conf`	A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end. ISPASS Gino Chacon, Nathan Gober, Krishnendra Nathella, Paul V. Gratz, Daniel A. Jiménez
2023	J	`jnl`	Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching. IEEE Comput. Archit. Lett. Daniel A. Jiménez, Elvira Teran, Paul V. Gratz
2023	—	`conf`	Rebasing Microarchitectural Research with Industry Traces. IISWC Josué Feliu, Arthur Perais, Daniel A. Jiménez, Alberto Ros
2022	C	`conf`	Composite Instruction Prefetching. ICCD Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul V. Gratz, Daniel A. Jiménez, Samira Mirbagher Ajorpaz
2022	C	`conf`	Dynamic Set Stealing to Improve Cache Performance. SBAC-PAD Brady Testa, Samira Mirbagher Ajorpaz, Daniel A. Jiménez
2022	A*	`conf`	Page Size Aware Cache Prefetching. MICRO Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jiménez, Marc Casas
2022	C	`conf`	SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches. ICCD Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez
2022	J	`jnl`	The Championship Simulator: Architectural Simulation for Education and Competition. CoRR Nathan Gober, Gino Chacon, Lei Wang, Paul V. Gratz, Daniel A. Jiménez, Elvira Teran, Seth H. Pugsley, Jinchun Kim
2022	A*	`conf`	Thermometer: profile-guided btb replacement for data center applications. ISCA Shixin Song, Tanvir Ahmed Khan, Sara Mahdizadeh-Shahri, Akshitha Sriraman, Niranjan K. Soundararajan, Sreenivas Subramoney, Daniel A. Jiménez, Heiner Litz, Baris Kasikci
2022	A*	`conf`	Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications. MICRO Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A. Jiménez, Baris Kasikci
2021	A*	`conf`	Exploiting Page Table Locality for Agile TLB Prefetching. ISCA Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Daniel A. Jiménez, Marc Casas
2021	A*	`conf`	Morrigan: A Composite Instruction TLB Prefetcher. MICRO Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jiménez, Marc Casas
2021	J	`jnl`	Top Picks From the 2020 Computer Architecture Conferences. IEEE Micro Daniel A. Jiménez
2020	A*	`conf`	CHiRP: Control-Flow History Reuse Prediction. MICRO Samira Mirbagher Ajorpaz, Elba Garza, Gilles Pokam, Daniel A. Jiménez
2020	—	`conf`	Characterizing the impact of last-level cache replacement policies on big-data workloads. IISWC Alexandre Valentin Jamet, Lluc Alvarez, Daniel A. Jiménez, Marc Casas
2020	A*	`conf`	Evolution of the Samsung Exynos CPU Microarchitecture. ISCA Brian Grayson, Jeff Rupley, Gerald D. Zuraski, Eric Quinnell, Daniel A. Jiménez, Tarun Nakra, Paul Kitchin, Ryan Hensley, Edward Brekelbaum, Vikas Sinha, Ankit Ghiya
2020	A	`conf`	LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. DATE Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
2020	A*	`conf`	PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron. MICRO Samira Mirbagher Ajorpaz, Gilles Pokam, Esmaeil Mohammadian Koruyeh, Elba Garza, Nael B. Abu-Ghazaleh, Daniel A. Jiménez
2020	A	`conf`	SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors. ICS Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez
2020	A*	`conf`	Support for Diverse Students. KDD Daniel A. Jiménez
2019	A*	`conf`	Bit-level perceptron prediction for indirect branches. ISCA Elba Garza, Samira Mirbagher Ajorpaz, Tahsin Ahmad Khan, Daniel A. Jiménez
2019	J	`jnl`	LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. CoRR Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Daniel Ödman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
2019	A*	`conf`	Perceptron-based prefetch filtering. ISCA Eshan Bhatia, Gino Chacon, Seth H. Pugsley, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez
2019	—	`conf`	The impact of cache inclusion policies on cache management techniques. MEMSYS Luna Backes, Daniel A. Jiménez
2018	A*	`conf`	Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. ISCA Samira Mirbagher Ajorpaz, Elba Garza, Sangam Jindal, Daniel A. Jiménez
2018	—	`conf`	Flexible associativity for DRAM caches. CF Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson, Daniel A. Jiménez
2018	J	`jnl`	MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. IEEE Comput. Archit. Lett. Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez
2017	A*	`conf`	Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. ASPLOS Jinchun Kim, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez, Seth H. Pugsley, Chris Wilkerson
2017	A*	`conf`	Multiperspective reuse prediction. MICRO Daniel A. Jiménez, Elvira Teran
2016	C	`conf`	Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie
2016	A*	`conf`	Minimal disturbance placement and promotion. HPCA Elvira Teran, Yingying Tian, Zhe Wang, Daniel A. Jiménez
2016	A*	`conf`	Perceptron learning for reuse prediction. MICRO Elvira Teran, Zhe Wang, Daniel A. Jiménez
2016	J	`jnl`	Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Trans. Archit. Code Optim. Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero
2015	—	`conf`	Adaptive GPU cache bypassing. GPGPU@PPoPP Yingying Tian, Sooraj Puthoor, Joseph L. Greathouse, Bradford M. Beckmann, Daniel A. Jiménez
2014	A*	`conf`	Adaptive placement and migration policy for an STT-RAM-based hybrid cache. HPCA Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie
2014	A*	`conf`	B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. MICRO David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel A. Jiménez
2014	A*	`conf`	Improving cache performance using read-write partitioning. HPCA Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, Daniel A. Jiménez
2014	A	`conf`	Last-level cache deduplication. ICS Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez, Gabriel H. Loh
2014	J	`jnl`	Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. IEEE Trans. Computers Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez
2013	A*	`conf`	Improving multi-core performance using mixed-cell cache architecture. HPCA Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep P. Kulkarni, Daniel A. Jiménez
2013	A*	`conf`	Insertion and promotion for tree-based PseudoLRU last-level caches. MICRO Daniel A. Jiménez
2013	J	`jnl`	Temporal-based multilevel correlating inclusive cache replacement. ACM Trans. Archit. Code Optim. Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez
2013	J	`jnl`	WADE: Writeback-aware dynamic cache management for NVM-based main memory system. ACM Trans. Archit. Code Optim. Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez
2012	J	`jnl`	B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. IEEE Comput. Archit. Lett. Reena Panda, Paul V. Gratz, Daniel A. Jiménez
2012	A*	`conf`	Decoupled dynamic cache segmentation. HPCA Samira Manabi Khan, Zhe Wang, Daniel A. Jiménez
2012	A*	`conf`	Improving writeback efficiency with decoupled last-write prediction. ISCA Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez
2012	—	`conf`	Rank idle time prediction driven last-level cache writeback. MSPC Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez
2011	C	`conf`	An optimized scaled neural branch predictor. ICCD Daniel A. Jiménez
2011	B	`conf`	Decoupled Cache Segmentation: Mutable Policy with Automated Bypass. PACT Samira Manabi Khan, Daniel A. Jiménez
2011	B	`conf`	Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback. PACT Zhe Wang, Daniel A. Jiménez
2011	B	`conf`	Program Interferometry. PACT Zhe Wang, Daniel A. Jiménez
2011	—	`conf`	Program Interferometry. IISWC Zhe Wang, Daniel A. Jiménez
2011	—	`conf`	Reducing network-on-chip energy consumption through spatial locality speculation. NOCS Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jiménez
2011	B	`conf`	Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy. PACT Yingying Tian, Daniel A. Jiménez
2010	C	`conf`	Insertion policy selection using Decision Tree Analysis. ICCD Samira Manabi Khan, Daniel A. Jiménez
2010	A*	`conf`	Sampling Dead Block Prediction for Last-Level Caches. MICRO Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez
2010	B	`conf`	Using dead blocks as a virtual victim cache. PACT Samira Manabi Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi
2009	J	`jnl`	Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. Trans. High Perform. Embed. Archit. Compil. Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
2009	C	`conf`	Composite Confidence Estimators for Enhanced Speculation Control. SBAC-PAD Daniel A. Jiménez
2009	J	`jnl`	Generalizing neural branch prediction. ACM Trans. Archit. Code Optim. Daniel A. Jiménez
2009	J	`jnl`	Mixed-Signal Approximate Computation: A Neural Predictor Case Study. IEEE Micro Renée St. Amant, Daniel A. Jiménez, Doug Burger
2008	A*	`conf`	A Two-Level Load/Store Queue Based on Execution Locality. ISCA Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero
2008	A*	`conf`	Low-power, high-performance analog neural branch prediction. MICRO Renée St. Amant, Daniel A. Jiménez, Doug Burger
2008	J	`jnl`	Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. Int. J. Parallel Program. Gabriel H. Loh, Daniel A. Jiménez
2007	B	`conf`	A Flexible Heterogeneous Multi-Core Architecture. PACT Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero
2007	J	`jnl`	An evaluation infrastructure for power and energy optimisations. Int. J. Embed. Syst. Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
2007	—	`conf`	Efficient Program Power Behavior Characterization. HiPEAC Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
2007	J	`jnl`	Guest Editor's Introduction. J. Instr. Level Parallelism Daniel A. Jiménez
2006	A*	`conf`	A decoupled KILO-instruction processor. HPCA Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero
2006	C	`conf`	Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. SBAC-PAD Daniel A. Jiménez, Gabriel H. Loh
2005	C	`conf`	Chained In-Order/Out-of-Order DoubleCore Architecture. SBAC-PAD Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez
2005	A*	`conf`	Code placement for improving dynamic branch prediction accuracy. PLDI Daniel A. Jiménez
2005	—	`conf`	Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. ISHPC Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero
2005	J	`jnl`	Idealized Piecewise Linear Branch Prediction. J. Instr. Level Parallelism Daniel A. Jiménez
2005	J	`jnl`	Improved latency and accuracy for neural branch prediction. ACM Trans. Comput. Syst. Daniel A. Jiménez
2005	A*	`conf`	Piecewise Linear Branch Prediction. ISCA Daniel A. Jiménez
2005	J	`jnl`	The Camino Compiler infrastructure. SIGARCH Comput. Archit. News Chunling Hu, John B. P. McCabe, Daniel A. Jiménez, Ulrich Kremer
2005	A	`conf`	Toward an Evaluation Infrastructure for Power and Energy Optimizations. IPDPS Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
2004	—	`conf`	Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. Interaction between Compilers and Computer Architectures Ravi V. Batchu, Daniel A. Jiménez
2003	A*	`conf`	Fast Path-Based Neural Branch Prediction. MICRO Daniel A. Jiménez
2003	A*	`conf`	Reconsidering Complex Branch Predictors. HPCA Daniel A. Jiménez
2002	J	`jnl`	Neural methods for dynamic branch prediction. ACM Trans. Comput. Syst. Daniel A. Jiménez, Calvin Lin
2001	—	`conf`	Boolean Formula-Based Branch Prediction for Future Technologies. IEEE PACT Daniel A. Jiménez, Heather L. Hanson, Calvin Lin
2001	A*	`conf`	Dynamic Branch Prediction with Perceptrons. HPCA Daniel A. Jiménez, Calvin Lin
2000	A*	`conf`	The impact of delay on the design of branch predictors. MICRO Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin