Dan Lei Yan

11 papers Journal 3Unranked 8
YearRankTypeTitle / Venue / Authors
2023 J jnl
A 35mW, 2.32dB NF, 1.1° Phase Error, 18-21.2GHz Beamforming Receiver IC for Satcom on the Move (SOTM) Phased Arrays.
IEEE Trans. Circuits Syst. II Express Briefs
Dan Lei Yan, Chan Kuen Sim, Hussain Ansari Md Arif, Nur Aisyah Binte Kuyob, M. Kumarasamy Raja, Kevin Tshun Chuan Chai
2017 — conf
A -121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT.
A-SSCC
M. Kumarasamy Raja, Zhao Bin, Dan Lei Yan, Hongbao Zhang, Wei Yi Lim, Leo John Chemmanda
2016 — conf
A 5.1Gb/s 60.3fJ/bit/mm PVT tolerant NoC transceiver.
A-SSCC
Vishal Vinayak Kulkarni, Wei Yi Lim, Bin Zhao, Dan Lei Yan, Yu-Shun Wang, Jun Zhou, Muthukumaraswamy Annamalai Arasu
2016 — conf
A low-power digital design of all digital PLL for 2.4G wireless communication applications.
ISIC
Bin Zhao, Dan Lei Yan
2016 J jnl
Digital Compensation Method for the Path Delay Mismatches in GRO-TDC.
J. Circuits Syst. Comput.
Pyoungwon Park, Dipankar Nag, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu
2014 — conf
A 400MHz low power fractional-N synthesizer with GFSK/GMSK modulation in 0.13μm CMOS.
ISIC
Dan Lei Yan, Zhao Bin, Atshushi Tamura, M. Kumarasamy Raja
2014 — conf
A fully integrated 166-GHz frequency synthesizer in 0.13-μm SiGe BiCMOS for D-band applications.
ISIC
Jin He, Yong-Zhong Xiong, Jian Kang Li, Debin Hou, Sanming Hu, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu, Yue Ping Zhang
2014 — conf
A fully integrated 166-GHz frequency synthesizer in 0.13-μm SiGe BiCMOS for D-band applications.
ISIC
Jin He, Yong-Zhong Xiong, Jiankang Li, Debin Hou, Sanming Hu, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu, Yue Ping Zhang
2014 — conf
Digital compensation method for the path delay mismatches in GRO-TDC.
ISIC
Pyoungwon Park, Dipankar Nag, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu
2008 J jnl
A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology.
IEEE J. Solid State Circuits
Pradeep Basappa Khannur, Xuesong Chen, Dan Lei Yan, Dan Shen, Bin Zhao, M. Kumarasamy Raja, Ye Wu, Rendra Sindunata, Wooi Gan Yeoh, Rajinder Singh
2007 — conf
A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS.
ESSCIRC
M. Kumarasamy Raja, Dan Lei Yan, Aruna B. Ajjikuttira