Dan Alexandrescu

62 papers A 4B 1C 23Misc 2Journal 16Unranked 16

Year	Rank	Type	Title / Venue / Authors
2023	Misc	`conf`	Innovation Practices Track: VLSI Functional Safety. VTS Fei Su, Meirav Nitzan, Ankush Sethi, Vaibhav Kumar, Dan Alexandrescu
2021	J	`jnl`	Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. CoRR Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2021	J	`jnl`	Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models. CoRR Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux
2021	—	`conf`	Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis. ISQED Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux
2021	J	`jnl`	Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. CoRR Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2021	—	`conf`	Modeling Soft-Error Reliability Under Variability. DFT Aneesh Balakrishnan, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu
2021	C	`conf`	On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. VLSI-SoC Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin
2021	J	`jnl`	The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. CoRR Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2020	—	`conf`	Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. MECO Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2020	C	`conf`	Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models. IOLTS Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux
2020	J	`jnl`	Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. CoRR Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020	C	`conf`	Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. IOLTS Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020	J	`jnl`	Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. CoRR Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020	J	`jnl`	Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. CoRR Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020	J	`jnl`	On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. CoRR Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2020	A	`conf`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2019	C	`ed.`	25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, Rhodes, Greece, July 1-3, 2019 IOLTS Dimitris Gizopoulos, Dan Alexandrescu, Panagiota Papavramidou, Michail Maniatakos
2019	—	`conf`	Challenges of Reliability Assessment and Enhancement in Autonomous Systems. DFT Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
2019	J	`jnl`	Challenges of Reliability Assessment and Enhancement in Autonomous Systems. CoRR Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
2019	—	`conf`	Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. DTIS Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2019	C	`conf`	Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. IOLTS Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2019	—	`conf`	Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. AHS Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2019	—	`conf`	On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. DSN (Supplements) Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
2019	J	`jnl`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2019	—	`conf`	The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. NORCAS Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2019	J	`jnl`	Understanding multidimensional verification: Where functional meets non-functional. Microprocess. Microsystems Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu
2018	C	`ed.`	24th IEEE International Symposium on On-Line Testing And Robust System Design, IOLTS 2018, Platja D'Aro, Spain, July 2-4, 2018 IOLTS Dimitris Gizopoulos, Dan Alexandrescu, Mihalis Maniatakos, Panagiota Papavramidou
2018	—	`conf`	A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. AHS Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs
2018	—	`conf`	Integrated Synthesis Methodology for Crossbar Arrays. NANOARCH Muhammed Ceylan Morgül, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, Elena-Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu
2017	C	`conf`	EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety. IOLTS Dan Alexandrescu, Adrian Evans, Maximilien Glorieux, Issam Nofal
2017	J	`jnl`	Logic synthesis and testing techniques for switching nano-crossbar arrays. Microprocess. Microsystems Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
2016	C	`conf`	Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer. DSD Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
2015	C	`conf`	A call for cross-layer and cross-domain reliability analysis and management. IOLTS Dan Alexandrescu, Adrian Evans, Enrico Costenaro, Maximilien Glorieux
2015	J	`jnl`	Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi
2015	—	`conf`	Techniques for heavy ion microbeam analysis of FPGA SER sensitivty. IRPS Adrian Evans, Dan Alexandrescu, Veronique Ferlet-Cavrois, Kay-Obbe Voss
2015	C	`conf`	The future of fault tolerant computing. IOLTS Jacob A. Abraham, Ravishankar K. Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian
2014	A	`conf`	Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales. DATE Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu
2014	C	`conf`	Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
2014	B	`conf`	Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation. ETS Dan Alexandrescu, Luca Sterpone, Celia López-Ongil
2014	A	`conf`	INFORMER: An integrated framework for early-stage memory robustness analysis. DATE Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio
2014	C	`conf`	Managing SER costs of complex systems through Linear Programming. IOLTS Dan Alexandrescu, Nematollah Bidokhti, Andy Yu, Adrian Evans, Enrico Costenaro
2014	C	`conf`	New approaches for synthesis of redundant combinatorial logic for selective fault tolerance. IOLTS Hao Xie, Li Chen, Rui Liu, Adrian Evans, Dan Alexandrescu, Shi-Jie Wen, Rick Wong
2013	J	`jnl`	A Practical Approach to Single Event Transient Analysis for Highly Complex Design. J. Electron. Test. Enrico Costenaro, Dan Alexandrescu, Kader Belhaddad, Michael Nicolaidis
2013	C	`conf`	Hierarchical RTL-based combinatorial SER estimation. IOLTS Adrian Evans, Dan Alexandrescu, Enrico Costenaro, Liang Chen
2013	—	`conf`	Pulse-length determination techniques in the rectangular single event transient fault model. ICSAMOS Alireza Rohani, Hans G. Kerkhoff, Enrico Costenaro, Dan Alexandrescu
2013	C	`conf`	State-aware single event analysis for sequential logic. IOLTS Dan Alexandrescu, Enrico Costenaro, Adrian Evans
2012	C	`conf`	A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. ICCD Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio
2012	C	`conf`	A real-case application of a synergetic design-flow-oriented SER analysis. IOLTS Miguel Vilchis, Ramnath Venkatraman, Enrico Costenaro, Dan Alexandrescu
2012	C	`conf`	RIIF - Reliability information interchange format. IOLTS Adrian Evans, Michael Nicolaidis, Shi-Jie Wen, Dan Alexandrescu, Enrico Costenaro
2012	J	`jnl`	Test methodology of a new upset mechanism induced by protons in deep sub-micron devices. Microelectron. Reliab. Cécile Weulersse, Florent Miller, Dan Alexandrescu, Erwin Schaefer, Olivier Crépel, Rémi Gaillard
2012	C	`conf`	Towards optimized functional evaluation of SEE-induced failures in complex designs. IOLTS Dan Alexandrescu, Enrico Costenaro
2011	—	`conf`	A Practical Approach to Single Event Transients Analysis for Highly Complex Designs. DFT Dan Alexandrescu, Enrico Costenaro, Michael Nicolaidis
2011	C	`conf`	A comprehensive soft error analysis methodology for SoCs/ASICs memory instances. IOLTS Dan Alexandrescu
2011	C	`conf`	A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. IOLTS Enrico Costenaro, Massimo Violante, Dan Alexandrescu
2010	A	`conf`	Panel: Reliability of data centers: Hardware vs. software. DATE Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota
2009	C	`conf`	Highs and lows of radiation testing. IOLTS Dan Alexandrescu, Anne-Lise Lhomme-Perrot, Erwin Schäfer, Cyrille Beltrando
2008	C	`conf`	A Systematical Method of Quantifying SEU FIT. IOLTS Shi-Jie Wen, Dan Alexandrescu, Renaud Perez
2008	Misc	`conf`	Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors. VTS Michael Nicolaidis, Renaud Perez, Dan Alexandrescu
2004	J	`jnl`	Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. J. Electron. Test. Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
2002	—	`conf`	New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. DFT Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
2002	—	`conf`	Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. LATW Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
2000	—	`conf`	Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy. SBCCI Lorena Anghel, Dan Alexandrescu, Michael Nicolaidis