Damu Radhakrishnan

19 papers A 1C 2Misc 2Journal 3Unranked 11
YearRankTypeTitle / Venue / Authors
2009 J jnl
Redundant binary partial product generators for compact accumulation in Booth multipliers.
Microelectron. J.
Bijoy Antony Jose, Damu Radhakrishnan
2008 J jnl
Delay Efficient 32-Bit Carry-Skip Adder.
VLSI Design
Yu Shen Lin, Damu Radhakrishnan
2006 — conf
Delay Efficient 32-bit Carry-Skip Adder.
ICECS
Yu Shen Lin, Damu Radhakrishnan
2006 — conf
Delay Optimized Redundant Binary Adders.
ICECS
Bijoy Antony Jose, Damu Radhakrishnan
2004 — conf
A Low Energy Deep Sub-Micron Bus Coding Technique.
ESA/VLSI
Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
2004 — conf
A Low-Power Pipelined Implementation of 2D Discrete Wavelet Transform.
ESA/VLSI
Yong Liu, Edmund Ming-Kit Lai, A. Benjamin Premkumar, Damu Radhakrishnan
2004 — conf
A Novel Bus Encoding Technique for Low Power VLSI.
ESA/VLSI
Jayapreetha Natesan, Damu Radhakrishnan
2004 — conf
Experimental Analysis of Batteries Under Continuous and Intermittent Operations.
ESA/VLSI
Smith Castillo, Naveen K. Samala, Kerron Manwaring, Baback A. Izadi, Damu Radhakrishnan
2004 C conf
Shift Invert Coding (SINV) for Low Power VLSI.
DSD
Jayapreetha Natesan, Damu Radhakrishnan
2004 — conf
Switching Activity Minimization in Combinational Logic Design.
ESA/VLSI
Rakesh Menon, Sarita Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
2003 — conf
Low-Power Dynamic Scheduling in Heterogeneous Systems.
Embedded Systems and Applications
Saumya Uppaluri, Baback A. Izadi, Damu Radhakrishnan
2003 — conf
Power Optimized Combinational Logic Design.
Embedded Systems and Applications
Rakesh Menon, Sarita Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
2001 — conf
A high performance RNS multiply-accumulate unit.
ACM Great Lakes Symposium on VLSI
Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi
2001 — conf
Fault-tolerance scheme for an RNS MAC: performance and cost analysis.
ISCAS (2)
Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi
2000 Misc conf
Pass logic circuits with reduced switching activity for low power DSP processors.
ICASSP
Damu Radhakrishnan
1999 J jnl
A Parallel Approach to Direct Analog-to-Residue Conversion.
Inf. Process. Lett.
Damu Radhakrishnan, Adimathara P. Preethy
1998 Misc conf
A new approach to data conversion: direct analog-to-residue converter.
ICASSP
Damu Radhakrishnan, Adimathara P. Preethy
1990 C conf
Fault tolerance in RNS: an efficient approach.
ICCD
Damu Radhakrishnan, Taejin Pyon
1985 A conf
Multiple Output Pass Networks: Design and Testing.
ITC
Ali Feizi, Damu Radhakrishnan