Damian Dalton

15 papers B 3C 3Misc 2Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2024 B conf
A Hybrid Deep Learning Approach for Modelling and Optimising Data Centre Energy Efficiency.
KES
Yibrah Gebreyesus, Damian Dalton, Davide De Chiara, Marta Chinnici
2023 J jnl
Machine Learning for Data Center Optimizations: Feature Selection Using Shapley Additive exPlanation (SHAP).
Future Internet
Yibrah Gebreyesus, Damian Dalton, Sebastian Nixon, Davide De Chiara, Marta Chinnici
2011 J jnl
Searching Extended IP-XACT Components for SoC Design Based on Requirements Similarity.
IEEE Syst. J.
Christoph Trummer, Christoph Ruggenthaler, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiß, Markus Pistauer, Damian Dalton
2010 J jnl
An IP-XACT Library extended with verification information for functionality-based component selection.
Elektrotech. Informationstechnik
Christoph Ruggenthaler, Christoph Trummer, Christian Steger, Reinhold Weiß, Andreas Schuhai, Markus Pistauer, Damian Dalton
2010 C conf
Automated simulation-based verification of power requirements for Systems-on-Chips.
DDECS
Christoph Trummer, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiss, Markus Pistauer, Damian Dalton
2005 — conf
Parallel Simulation with a Generic Simulation Framework Featuring Loose Coupling.
ICPP Workshops
Mario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher
2005 — conf
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator.
ISVLSI
Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton
2004 C conf
A Generic Simulation Framework for Multiprocessor Architectures.
FDL
Mario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher
2004 — conf
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.
PATMOS
Alexander Maili, Damian Dalton, Christian Steger
2003 B conf
APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator.
FPL
Damian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O'Kane, Rob Quigley, Declan O'Connor
1999 Misc conf
A New Timing Mechanism Architecture for Discrete Logic Event Simulation.
PDPTA
Damian Dalton
1999 C conf
A special purpose hybrid SIMD processor for logic event simulation.
PDP
Damian Dalton
1999 — conf
Analysis of an Associative Array Parallel Logic Simulator.
ICPP Workshops
Damian Dalton
1999 Misc conf
Avoiding Conventional Overheads in Parallel Logic Simulation: A New Architecture.
HiPC
Damian Dalton
1999 B conf
The Speedup Performance of an Associative Memory Based Logic Simulator.
PaCT
Damian Dalton