Dake Liu - RankMe

124 papers A 2B 7C 16Misc 4Journal 45Unranked 48

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Efficient Instruction Fusion for ASIPs: A Low-Cost Approach to Structural Hazard Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xinbing Zhou, Tianlang Liu, Tiancheng Tang, Yi Man, Peng Hao, Wei Chen, Dake Liu
2026	J	`jnl`	Efficient and Flexible Deep Learning Processor for Embedded Devices With 99.8% PE Utilization Under Low Silicon Cost. IEEE Trans. Circuits Syst. I Regul. Pap. Wei Chen, Dake Liu, Yueming Hu
2026	J	`jnl`	Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing. ACM Trans. Embed. Comput. Syst. Xinbing Zhou, Shaobo Shi, Shaohan Liu, Peng Hao, Yunxiang Tang, Tiancheng Tang, Yi Man, Dake Liu
2025	J	`jnl`	AIKII: An AI-Enhanced Knowledge Interactive Interface for Knowledge Representation in Educational Games. Comput. Animat. Virtual Worlds Dake Liu, Huiwen Zhao, Wen Tang, Wenwen Yang
2025	J	`jnl`	Hardware Sharing Design Method of Rate Matching and Interleaving for Wireless Terminal in Industrial Internet of Things. IEEE Internet Things J. Wei Chen, Kejia Huo, Dake Liu
2025	J	`jnl`	High-Throughput LDPC Decoder for Multiple Wireless Standards. IEEE Trans. Circuits Syst. I Regul. Pap. Wei Chen, Yajie Li, Dake Liu
2025	J	`jnl`	Task Scheduling for Heterogeneous Multi-Core Processors Based on Deep Reinforcement Learning. Int. J. Intell. Syst. Qiguang Tan, Wei Chen, Dake Liu
2024	J	`jnl`	B5G/6G URLLC Latency Reduction Method for Multisensor Industrial Internet of Things. IEEE Internet Things J. Wei Chen, Dake Liu, Yong Bai
2024	J	`jnl`	Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei Chen, Dake Liu
2023	—	`conf`	TAPE: Tangible Augmented Previz Environment for Filmmaking. CCHI Guangzheng Fei, Dake Liu
2022	J	`jnl`	An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost. Sensors Muxuan Gao, He Chen, Dake Liu
2022	J	`jnl`	An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells. Sensors Biao Long, Dake Liu, Yipeng Sun
2022	J	`jnl`	Compilation of Parallel Data Access for Vector Processor in Radio Base Stations. IEEE Embed. Syst. Lett. Wei Chen, Peng Hao, Dake Liu, Yong Bai
2022	J	`jnl`	Detector Processor for a 5G Base Station. Sensors Cao Niu, Dake Liu
2021	J	`jnl`	An ASIP design for low loss compression of front-haul data in 5G base stations. IEICE Electron. Express Yunxiang Tang, Biao Long, Dake Liu
2021	J	`jnl`	Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations. IEEE Access Wei Chen, Dake Liu, Yong Bai, Rifei Yang
2021	J	`jnl`	Hardware Sharing for Channel Interleavers in 5G NR Standard. Secur. Commun. Networks Xiaokang Xiong, Yuhang Dai, Zhuhua Hu, Kejia Huo, Yong Bai, Hui Li, Dake Liu
2021	J	`jnl`	Low-Latency QC-LDPC Encoder Design for 5G NR. Sensors Yunke Tian, Yong Bai, Dake Liu
2019	J	`jnl`	A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. IEEE Trans. Very Large Scale Integr. Syst. Shaohan Liu, Dake Liu
2018	J	`jnl`	Design Space Exploration of 1-D FFT Processor. J. Signal Process. Syst. Shaohan Liu, Dake Liu
2018	J	`jnl`	High-throughput bit processor for cryptography, error correction, and error detection. Microprocess. Microsystems Yuanhong Huo, Dake Liu
2018	J	`jnl`	QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding. IEEE Access Wan Qiao, Dake Liu, Shaohan Liu
2017	C	`conf`	A 3-coil simultaneous power and uplink data transmission inductive link for battery-less implantable devices. ISCAS Min Li, Dake Liu, Chen Gong, Wan Qiao
2017	J	`jnl`	A Magnetic-Balanced Inductive Link for the Simultaneous Uplink Data and Power Telemetry. Sensors Chen Gong, Dake Liu, Zhidong Miao, Min Li
2017	J	`jnl`	An Adaptive Impedance Matching Network with Closed Loop Control Algorithm for Inductive Wireless Power Transfer. Sensors Zhidong Miao, Dake Liu, Chen Gong
2017	J	`jnl`	An NFC on Two-Coil WPT Link for Implantable Biomedical Sensors under Ultra-Weak Coupling. Sensors Chen Gong, Dake Liu, Zhidong Miao, Wei Wang, Min Li
2017	J	`jnl`	Computational Complexity Analysis of FEC Decoding on SDR Platforms. J. Signal Process. Syst. Zhenzhi Wu, Chen Gong, Dake Liu
2017	J	`jnl`	Efficiency Enhancement for an Inductive Wireless Power Transfer System by Optimizing the Impedance Matching Networks. IEEE Trans. Biomed. Circuits Syst. Zhidong Miao, Dake Liu, Chen Gong
2017	—	`conf`	High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms. ASAP Yuanhong Huo, Dake Liu
2016	J	`jnl`	A High-Throughput Processor for Cryptographic Hash Functions. J. Commun. Yuanhong Huo, Dake Liu
2016	—	`conf`	A digital crystal-less clock generation scheme for wireless biomedical implants. BioCAS Hongxia Luo, Dake Liu, Chen Gong, Min Li
2015	—	`conf`	A contention-free memory subsystem for 5G Turbo decoder with flexible degree of parallelism. SiPS Zhenzhi Wu, Dake Liu, Xiaoyang Li, Chen Gong
2015	—	`conf`	A novel transcutaneous NFC uplink system symbiotic with inductive wireless power supply under ultra low coupling coefficient. BioCAS Chen Gong, Dake Liu, Zhidong Miao, Huahong Zhang
2015	—	`conf`	An optimizing procedure of the wireless power transfer link for an intraocular implantable device. BMEI Zhidong Miao, Dake Liu, Chen Gong
2015	C	`conf`	Benefit and cost of cross sliding window scheduling for low latency 5G Turbo decoding. ICCC Dake Liu, Chaoyuan Zuo, Zhenzhi Wu
2015	—	`conf`	Combined RF and multiphase PWM transmitter. ECCTD Muhammad Fahim Ul Haque, Ted Johansson, Dake Liu
2015	—	`conf`	Cost-efficient mapping of 3- and 5-point DFTs to general baseband processors. DSP Andreas Karlsson, Joar Sohl, Dake Liu
2015	—	`conf`	Energy-Efficient Sorting with the Distributed Memory Architecture ePUMA. TrustCom/BigDataSE/ISPA (3) Andreas Karlsson, Joar Sohl, Dake Liu
2015	C	`conf`	High performance table-based architecture for parallel CRC calculation. LANMAN Yuanhong Huo, Xiaoyang Li, Wei Wang, Dake Liu
2015	J	`jnl`	High-Throughput Trellis Processor for Multistandard FEC Decoding. IEEE Trans. Very Large Scale Integr. Syst. Zhenzhi Wu, Dake Liu
2015	—	`conf`	Loop acceleration and instruction repeat support for application specific instruction-set processors. SoCC Zhenzhi Wu, Dake Liu, Xiaoyang Li
2015	—	`conf`	Software-based QPP interleaving for baseband DSPs with LUT-accelerated addressing. DSP Andreas Karlsson, Joar Sohl, Dake Liu
2015	J	`jnl`	Virtual RATs and a flexible and tailored radio access network evolving to 5G. IEEE Commun. Mag. Shanzhi Chen, Jian Zhao, Ming Ai, Dake Liu, Ying Peng
2015	—	`conf`	ePUMA: A processor architecture for future DSP. DSP Andreas Karlsson, Joar Sohl, Dake Liu
2014	J	`jnl`	A Vision of IoT: Applications, Challenges, and Opportunities With China Perspective. IEEE Internet Things J. Shanzhi Chen, Hui Xu, Dake Liu, Bo Hu, Hucheng Wang
2014	—	`conf`	A conflict-free access method for parallel turbo decoder. WCSP Chen Gong, Xiaoyang Li, Zhenzhi Wu, Dake Liu
2014	J	`jnl`	Comprehensive Performance Analysis of Two-Way Multi-Relay System with Amplify-and-Forward Relaying. IEICE Trans. Commun. Siye Wang, Yanjun Zhang, Bo Zhou, Wenbiao Zhou, Dake Liu
2014	B	`conf`	FPGA implementation of a multi-algorithm parallel FEC for SDR platforms. FPL Zhenzhi Wu, Dake Liu, Zheng Yang, Qingying Wang, Wei Zhou
2014	—	`conf`	Flexible multistandard FEC processor design with ASIP methodology. ASAP Zhenzhi Wu, Dake Liu
2014	C	`conf`	Matrix reordering techniques for memory conflict reduction for pipelined QC-LDPC decoder. ICCC Zhenzhi Wu, Dake Liu, Yanjun Zhang
2014	—	`conf`	Memory sharing techniques for multi-standard high-throughput FEC decoder. ICSAMOS Zhenzhi Wu, Dake Liu
2014	—	`conf`	Recognition of access patterns for DSP kernel codes. ICSAI Xiaoyang Li, Yu Liu, Chen Gong, Dake Liu
2013	—	`ch.`	Application Specific Instruction Set DSP Processors. Handbook of Signal Processing Systems Dake Liu, Jian Wang
2013	—	`conf`	Combined RF and multilevel PWM switch mode power amplifier. NORCHIP Muhammad Fahim Ul Haque, Ted Johansson, Dake Liu
2013	Misc	`conf`	Conflict-free data access for multi-bank memory architectures using padding. HiPC Joar Sohl, Jian Wang, Andreas Karlsson, Dake Liu
2013	J	`jnl`	Efficient sorting design on a novel embedded parallel computing architecture with unique memory access. Comput. Electr. Eng. Wenbiao Zhou, Zhaoyun Cai, Ruiqiang Ding, Chen Gong, Dake Liu
2013	J	`jnl`	Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems. IET Wirel. Sens. Syst. Xu Yang, Yanjun Zhang, Dake Liu, Deyuan Guo, Hu He
2013	—	`conf`	ePUMA: A unique memory access based parallel DSP processor for SDR and CR. GlobalSIP Andreas Karlsson, Joar Sohl, Jian Wang, Dake Liu
2012	C	`conf`	Automatic Permutation for Arbitrary Static Access Patterns. ISPA Joar Sohl, Jian Wang, Andreas Karlsson, Dake Liu
2012	—	`conf`	Automatic Synthesizable HDL Generator for NoGAP. ACIS-ICIS Wenbiao Zhou, Per Karlström, Dake Liu
2012	C	`conf`	Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory. DSD Jian Wang, Andreas Karlsson, Joar Sohl, Dake Liu
2012	J	`jnl`	Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support. J. Signal Process. Syst. Rizwan Asghar, Di Wu, Ali Saeed, Yulin Huang, Dake Liu
2011	—	`conf`	A multi-level arbitration and topology free streaming network for chip multiprocessor. ASICON Jian Wang, Andreas Karlsson, Joar Sohl, Magnus Pettersson, Dake Liu
2011	Misc	`conf`	An Efficient Streaming Star Network for Multi-core Parallel DSP Processor. ICNC Jian Wang, Joar Sohl, Andreas Karlsson, Dake Liu
2011	Misc	`conf`	Case Study of Efficient Parallel Memory Access Programming for the Embedded Heterogeneous Multicore DSP Architecture ePUMA. CISIS Erik Hansson, Joar Sohl, Christoph W. Kessler, Dake Liu
2011	—	`conf`	Implementation Aspects of Channel Estimation for 3GPP LTE Terminals. EW Michal Simko, Di Wu, Christian Mehlführer, Johan Eilert, Dake Liu
2011	J	`jnl`	Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio. J. Signal Process. Syst. Di Wu, Johan Eilert, Dake Liu
2011	C	`conf`	ePUMA embedded parallel DSP processor with Unique Memory Access. ICICS Dake Liu, Andreas Karlsson, Joar Sohl, Jian Wang, Magnus Pettersson, Wenbiao Zhou
2010	—	`ch.`	Application Specific Instruction Set DSP Processors. Handbook of Signal Processing Systems Dake Liu
2010	C	`conf`	Architectural Support for Reducing Parallel Processing Overhead in an Embedded Multiprocessor. EUC Jian Wang, Joar Sohl, Dake Liu
2010	—	`conf`	Automatic port and bus sizing in NoGap. ICSAMOS Per Karlström, Wenbiao Zhou, Dake Liu
2010	C	`conf`	Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study. EUC Per Karlström, Wenbiao Zhou, Dake Liu
2010	J	`jnl`	Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding. J. Signal Process. Syst. Rizwan Asghar, Di Wu, Johan Eilert, Dake Liu
2010	J	`jnl`	Multimode Flex-Interleaver Core for Baseband Processor Platform. J. Comput. Networks Commun. Rizwan Asghar, Dake Liu
2010	C	`conf`	NoGap DDECS Wenbiao Zhou, Per Karlström, Dake Liu
2010	—	`conf`	Operation Classification for Control Path Synthetization with NoGAP. ITNG Per Karlström, Wenbiao Zhou, Dake Liu
2010	J	`jnl`	Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels. Int. J. Embed. Real Time Commun. Syst. Dake Liu, Joar Sohl, Jian Wang
2010	C	`conf`	Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors. DSD Jian Wang, Joar Sohl, Olof Kraigher, Dake Liu
2010	J	`jnl`	System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor. Int. J. Embed. Real Time Commun. Syst. Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu, Anders Nilsson, Eric Tell, Eric Alfredsson
2010	J	`jnl`	VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless. EURASIP J. Wirel. Commun. Netw. Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu
2010	—	`conf`	VLSI implementation of A multi-standard MIMO symbol detector for 3GPP LTE and WiMAX. WTS Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu, Magic Ge
2009	J	`jnl`	An 11 mm IEEE J. Solid State Circuits Anders Nilsson, Eric Tell, Dake Liu
2009	B	`conf`	An ASIC perspective on FPGA optimizations. FPL Andreas Ehliar, Dake Liu
2009	J	`jnl`	Bridging dream and reality: Programmable baseband processors for software-defined radio. IEEE Commun. Mag. Dake Liu, Anders Nilsson, Eric Tell, Di Wu, Johan Eilert
2009	—	`conf`	Evaluation of MIMO symbol detectors for 3GPP LTE terminals. EUSIPCO Di Wu, Johan Eilert, Dake Liu
2009	—	`conf`	Implementation Aspects of Fixed-Complexity Soft-Output MIMO Detection. VTC Spring Di Wu, Erik G. Larsson, Dake Liu
2009	—	`conf`	Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture. APPT Joar Sohl, Jian Wang, Dake Liu
2009	C	`conf`	Low Complexity Hardware Interleaver for MIMO-OFDM based Wireless LAN. ISCAS Rizwan Asghar, Dake Liu
2009	C	`conf`	Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution. DSD Rizwan Asghar, Di Wu, Johan Eilert, Dake Liu
2009	—	`conf`	NoGAP: A Micro Architecture Construction Framework. SAMOS Per Karlström, Dake Liu
2009	—	`conf`	System architecture for 3GPP LTE modem using a programmable baseband processor. SoC Di Wu, Johan Eilert, Dake Liu, Anders Nilsson, Eric Tell, Eric Alfredsson
2008	B	`conf`	A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. FPL Andreas Ehliar, Per Karlström, Dake Liu
2008	—	`conf`	An 11mm ISSCC Anders Nilsson, Eric Tell, Dake Liu
2008	B	`conf`	Cost Analysis of Channel Estimation in MIMO-OFDM for Software Defined Radio. WCNC Qi Wang, Di Wu, Johan Eilert, Dake Liu
2008	—	`conf`	Dual standard re-configurable hardware interleaver for turbo decoding. ISWPC Rizwan Asghar, Dake Liu
2008	J	`jnl`	High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. IET Comput. Digit. Tech. Per Karlström, Andreas Ehliar, Dake Liu
2008	Misc	`conf`	Implementation of a programmable linear MMSE detector for MIMO-OFDM. ICASSP Johan Eilert, Di Wu, Dake Liu
2007	B	`conf`	An fpga based open source network-on-chip architecture. FPL Andreas Ehliar, Dake Liu
2007	—	`conf`	Area Efficient Fully Programmable Baseband Processors. SAMOS Anders Nilsson, Dake Liu
2007	C	`conf`	Efficient Complex Matrix Inversion for MIMO Software Defined Radio. ISCAS Johan Eilert, Di Wu, Dake Liu
2007	—	`conf`	Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding. ISVLSI Di Wu, Johan Eilert, Dake Liu, Dandan Wang, Naofal Al-Dhahir, Hlaing Minn
2007	B	`conf`	Lattice-Reduction Aided Multi-User STBC Decoding with Resource Constraints. PIMRC Di Wu, Johan Eilert, Dake Liu
2006	—	`conf`	A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms. ARCS Workshops Di Wu, Tiejun Hu, Dake Liu
2006	A	`conf`	Accelerating CABAC encoding for multi-standard media with configurability. IPDPS Oskar Flordal, Di Wu, Dake Liu
2006	B	`conf`	MIPS cost estimation for OFDM-VBLAST systems. WCNC Haiyan Jiao, Anders Nilsson, Eric Tell, Dake Liu
2005	—	`conf`	A Low Area and Low Power Programmable Baseband Processor Architecture. IWSOC Eric Tell, Anders Nilsson, Dake Liu
2005	—	`conf`	A programmable SIMD-based multi-standard Rake receiver architecture. EUSIPCO Anders Nilsson, Eric Tell, Dake Liu
2005	—	`conf`	Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. IWSOC Daniel Wiklund, Dake Liu
2005	—	`conf`	Flexible route lookup using range search. Communications and Computer Networks Andreas Ehliar, Dake Liu
2004	—	`conf`	Bit Memory Instructions for a General CPU. IWSOC Mikael Olausson, Anders Edman, Dake Liu
2004	—	`conf`	Design of a guaranteed throughput router for on-chip networks. SoC Sumant Sathe, Daniel Wiklund, Dake Liu
2004	—	`conf`	Network on Chip Simulations for Benchmarking. IWSOC Daniel Wiklund, Sumant Sathe, Dake Liu
2004	—	`conf`	Network processors for access network (NP4AN): trends and challenges. SoCC Xiaoning Nie, Ulf Nordqvist, Lajos Gazsi, Dake Liu
2004	—	`conf`	Reduced floating point for MPEG1/2 layer III decoding. ICASSP (5) Mikael Olausson, Andreas Ehliar, Johan Eilert, Dake Liu
2004	C	`conf`	Using low precision floating point numbers to reduce memory cost for MP3 decoding. MMSP Johan Eilert, Andreas Ehliar, Dake Liu
2003	—	`conf`	A converged hardware solution for FFT, DCT and Walsh transform. ISSPA (1) Eric Tell, Olle Seger, Dake Liu
2003	—	`conf`	A general DSP processor at the cost of 23K gates and 1/2 a man-year design time. ICASSP (2) Eric Tell, Mikael Olausson, Dake Liu
2003	—	`conf`	Implementation of fast CRC calculation. ASP-DAC Tomas Henriksson, Dake Liu
2003	—	`conf`	Power optimized packet buffering in a protocol processor. ICECS Ulf Nordqvist, Dake Liu
2003	A	`conf`	SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems. IPDPS Daniel Wiklund, Dake Liu
2002	C	`conf`	Embedded Protocol Processor for Fast and Efficient Packet Reception. ICCD Tomas Henriksson, Ulf Nordqvist, Dake Liu
2001	—	`conf`	VLSI implementation of CRC-32 for 10 Gigabit Ethernet. ICECS Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors, Dake Liu
1994	J	`jnl`	Power consumption estimation in CMOS VLSI chips. IEEE J. Solid State Circuits Dake Liu, Christer Svensson
1993	J	`jnl`	Trading speed for low power by choice of supply and threshold voltages. IEEE J. Solid State Circuits Dake Liu, Christer Svensson