Dajiang Zhou - RankMe

121 papers A* 3A 6B 8C 20Misc 2Journal 52Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	OmniZip: Learning a Unified and Lightweight Lossless Compressor for Multi-Modal Data. CoRR Yan Zhao, Zhengxue Cheng, Junxuan Zhang, Dajiang Zhou, Qunshan Gu, Qi Wang, Li Song
2025	A*	`conf`	L3TC: Leveraging RWKV for Learned Lossless Low-Complexity Text Compression. AAAI Junxuan Zhang, Zhengxue Cheng, Yan Zhao, Shihao Wang, Dajiang Zhou, Guo Lu, Li Song
2025	A*	`conf`	Multi-Frame Deformable Look-Up Table for Compressed Video Quality Enhancement. AAAI Gang He, Guancheng Quan, Chang Wu, Shihao Wang, Dajiang Zhou, Yunsong Li
2025	Misc	`conf`	PQNAS: Mixed-precision Quantization-aware Neural Architecture Search with Pseudo Quantizer. ICASSP Tianxiao Gao, Li Guo, Shihao Wang, Shiai Zhu, Dajiang Zhou
2025	A*	`conf`	RivuletMLP: An MLP-based Architecture for Efficient Compressed Video Quality Enhancement. CVPR Gang He, Weiran Wang, Guancheng Quan, Shihao Wang, Dajiang Zhou, Yunsong Li
2024	J	`jnl`	Beyond Feature Mapping GAP: Integrating Real HDRTV Priors for Superior SDRTV-to-HDRTV Conversion. CoRR Kepeng Xu, Li Xu, Gang He, Zhiqiang Zhang, Wenxin Yu, Shihao Wang, Dajiang Zhou, Yunsong Li
2024	J	`jnl`	L3TC: Leveraging RWKV for Learned Lossless Low-Complexity Text Compression. CoRR Junxuan Zhang, Zhengxue Cheng, Yan Zhao, Shihao Wang, Dajiang Zhou, Guo Lu, Li Song
2024	—	`conf`	QuantNAS: Quantization-aware Neural Architecture Search For Efficient Deployment On Mobile Device. CVPR Workshops Tianxiao Gao, Li Guo, Shanwei Zhao, Peihan Xu, Yukun Yang, Xionghao Liu, Shihao Wang, Shiai Zhu, Dajiang Zhou
2023	C	`conf`	A High Resolution SAR Imaging Method for Moving Target Based on Range Doppler and Particle Swarm Optimization Algorithm. IGARSS Dajiang Zhou, Hanqing Zhu, Yulin Huang, Yongchao Zhang, Jianyu Yang, Qingying Yi
2023	—	`conf`	Efficient Deep Models for Real-Time 4K Image Super-Resolution. NTIRE 2023 Benchmark and Report. CVPR Workshops Marcos V. Conde, Eduard Zamfir, Radu Timofte, Daniel Motilla, Cen Liu, Zexin Zhang, Yunbo Peng, Yue Lin, Jiaming Guo, Xueyi Zou, Yuyi Chen, Yi Liu, Jia Hao, Youliang Yan, Yuanfan Zhang, Gen Li, Lei Sun, Lingshun Kong, Haoran Bai, Jinshan Pan, Jiangxin Dong, Jinhui Tang, Mustafa Ayazoglu, Bahri Batuhan Bilecen, Mingxi Li, Yuhang Zhang, Xianjun Fan, Yankai Sheng, Long Sun, Zibin Liu, Weiran Gou, Shaoqing Li, Ziyao Yi, Yan Xiang, Dehui Kong, Ke Xu, Ganzorig Gankhuyag, Kihwan Yoon, Jin Zhang, Gaocheng Yu, Feng Zhang, Hongbin Wang, Zhou Zhou, Jiahao Chao, Hongfan Gao, Jiali Gong, Zhengfeng Yang, Zhenbing Zeng, Chengpeng Chen, Zichao Guo, Anjin Park, Yuqing Liu, Qi Jia, Hongyuan Yu, Xuanwu Yin, Dongyang Zhang, Ting Fu, Zhengxue Cheng, Shiai Zhu, Dajiang Zhou, Weichen Yu, Lin Ge, Jiahua Dong, Yajun Zou, Zhuoyuan Wu, Binnan Han, Xiaolin Zhang, Heng Zhang, Ben Shao, Shaolong Zheng, Daheng Yin, Baijun Chen, Mengyang Liu, Marian-Sergiu Nistor, Yi-Chung Chen, Zhi-Kai Huang, Yuan-Chun Chiang, Wei-Ting Chen, Hao-Hsiang Yang, Hua-En Chang, I-Hsiang Chen, Chia-Hsuan Hsieh, Sy-Yen Kuo, Tu Vo, Qingsen Yan, Yun Zhu, Jinqiu Su, Yanning Zhang, Cheng Zhang, Jiaying Luo, Youngsun Cho, Nakyung Lee, Kunlong Zuo
2023	C	`conf`	Moving Target Detection Method for Passive Radar Using LEO Communication Satellite Constellation. IGARSS Hanqing Zhu, Dajiang Zhou, Zhongyu Li, Hongyang An, Chuan Huang, Yun Zhou, Jianyu Yang
2021	—	`conf`	Perceptual Image Compression Using Relativistic Average Least Squares GANs. CVPR Workshops Zhengxue Cheng, Ting Fu, Jiapeng Hu, Li Guo, Shihao Wang, Xiongxin Zhao, Dajiang Zhou, Yang Song
2018	J	`jnl`	A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. IEEE Trans. Circuits Syst. Video Technol. Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, Satoshi Goto
2018	J	`jnl`	Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing. IEICE Trans. Electron. Jian-Bin Zhou, Dajiang Zhou, Takeshi Yoshimura, Satoshi Goto
2018	C	`conf`	Embedded Frame Compression for Energy-Efficient Computer Vision Systems. ISCAS Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
2018	J	`jnl`	Lossy Compression for Embedded Computer Vision Systems. IEEE Access Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura, Satoshi Goto
2018	—	`conf`	Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. ASP-DAC Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura
2018	C	`conf`	Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression. ISCAS Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
2017	—	`conf`	100x Evolution of Video Codec Chips. ISPD Jinjia Zhou, Dajiang Zhou, Satoshi Goto
2017	J	`jnl`	A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor. IEICE Trans. Electron. Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2017	J	`jnl`	A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding. IEEE Trans. Very Large Scale Integr. Syst. Jian-Bin Zhou, Dajiang Zhou, Shihao Wang, Shuping Zhang, Takeshi Yoshimura, Satoshi Goto
2017	J	`jnl`	Accelerating HEVC Inter Prediction with Improved Merge Mode Handling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura
2017	J	`jnl`	An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. IEEE J. Solid State Circuits Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
2017	C	`conf`	Approximate-DCT-derived measurement matrices for compressed sensing. ISCAS Jian-Bin Zhou, Dajiang Zhou, Takeshi Yoshimura, Satoshi Goto
2017	J	`jnl`	CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Networks. CoRR Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura
2017	J	`jnl`	Chain-NN: An Energy-Efficient 1D Chain Architecture for Accelerating Deep Convolutional Neural Networks. CoRR Shihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura
2017	A	`conf`	Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks. DATE Shihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura
2017	J	`jnl`	Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2017	J	`jnl`	Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC. IEEE Trans. Multim. Heming Sun, Dajiang Zhou, Landan Hu, Shinji Kimura, Satoshi Goto
2017	J	`jnl`	Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jian-Bin Zhou, Dajiang Zhou, Li Guo, Takeshi Yoshimura, Satoshi Goto
2017	C	`conf`	Measurement-domain intra prediction framework for compressively sensed images. ISCAS Jian-Bin Zhou, Dajiang Zhou, Li Guo, Takeshi Yoshimura, Satoshi Goto
2017	J	`jnl`	VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications. IEEE Trans. Circuits Syst. Video Technol. Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto
2016	—	`conf`	14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. ISSCC Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
2016	J	`jnl`	A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Heming Sun, Dajiang Zhou, Shuping Zhang, Shinji Kimura
2016	C	`conf`	CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks. ICCD Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura
2016	—	`conf`	Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. ICME Workshops Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2016	J	`jnl`	Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. CoRR Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2016	J	`jnl`	HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip. IEICE Electron. Express Zhenqi Wei, Peilin Liu, Rongdi Sun, Zunquan Zhou, Ke Jin, Dajiang Zhou
2015	J	`jnl`	A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. IEEE Trans. Very Large Scale Integr. Syst. Jinjia Zhou, Dajiang Zhou, Jiayi Zhu, Satoshi Goto
2015	C	`conf`	A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio. ISCAS Jinjia Zhou, Yizhou Zou, Dajiang Zhou, Satoshi Goto
2015	—	`conf`	A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi. ASICON Wenchao Zhang, Song Chen, Xuefei Bai, Dajiang Zhou
2015	C	`conf`	An independent bandwidth reduction device for HEVC VLSI video system. ISCAS Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2015	—	`conf`	Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder. ICME Workshops Landan Hu, Heming Sun, Dajiang Zhou, Shinji Kimura
2015	J	`jnl`	High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jian-Bin Zhou, Dajiang Zhou, Shihao Wang, Takeshi Yoshimura, Satoshi Goto
2015	J	`jnl`	High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding. IEEE Trans. Very Large Scale Integr. Syst. Gang He, Dajiang Zhou, Yunsong Li, Zhixiang Chen, Tianruo Zhang, Satoshi Goto
2015	J	`jnl`	Low-Power Motion Estimation Processor with 3D Stacked Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2015	C	`conf`	Merge mode based fast inter prediction for HEVC. VCIP Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura
2015	J	`jnl`	Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications. IEEE Trans. Circuits Syst. Video Technol. Dajiang Zhou, Jinjia Zhou, Wei Fei, Satoshi Goto
2015	J	`jnl`	Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto
2014	J	`jnl`	A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder. IEEE J. Solid State Circuits Dajiang Zhou, Jinjia Zhou, Gang He, Satoshi Goto
2014	B	`conf`	A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications. ICIP Yijin Zhao, Jinjia Zhou, Dajiang Zhou, Satoshi Goto
2014	J	`jnl`	A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Heming Sun, Dajiang Zhou, Peilin Liu, Satoshi Goto
2014	J	`jnl`	A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec. IEEE Trans. Multim. Li Guo, Dajiang Zhou, Satoshi Goto
2014	C	`conf`	A low power 720p motion estimation processor with 3D stacked memory. VLSI-SoC Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto
2014	J	`jnl`	Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC. J. Vis. Commun. Image Represent. Jinjia Zhou, Dajiang Zhou, Satoshi Goto
2014	C	`conf`	An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder. VCIP Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto
2014	J	`jnl`	Fast Prediction Unit Selection and Mode Selection for HEVC Intra Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Heming Sun, Dajiang Zhou, Peilin Liu, Satoshi Goto
2014	J	`jnl`	Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2014	B	`conf`	Fast SAO estimation algorithm and its VLSI architecture. ICIP Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2014	J	`jnl`	High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications. IEEE Trans. Very Large Scale Integr. Syst. Gang He, Dajiang Zhou, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto
2014	—	`conf`	Live demonstration: FPGA based 3840×2160 video decoding and displaying system. APCCAS Haoming Zhang, Dajiang Zhou, Satoshi Goto
2014	—	`conf`	Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction. MMM (1) Zhe Sheng, Dajiang Zhou, Heming Sun, Satoshi Goto
2014	A	`conf`	Motion compensation architecture for 8K UHDTV HEVC decoder. ICME Shihao Wang, Dajiang Zhou, Satoshi Goto
2014	B	`conf`	OpenCL based high-quality HEVC motion estimation on GPU. ICIP Fan Wang, Dajiang Zhou, Satoshi Goto
2014	B	`conf`	Reducing power consumption of HEVC codec with lossless reference frame recompression. ICIP Dajiang Zhou, Li Guo, Jinjia Zhou, Satoshi Goto
2014	—	`conf`	Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder. PCM Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto
2014	B	`conf`	VLSI architecture of HEVC intra prediction for 8K UHDTV applications. ICIP Jian-Bin Zhou, Dajiang Zhou, Heming Sun, Satoshi Goto
2013	—	`conf`	A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS. ASP-DAC Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto
2013	J	`jnl`	A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto
2013	—	`conf`	A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. ASP-DAC Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto
2013	J	`jnl`	A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Muchen Li, Jinjia Zhou, Dajiang Zhou, Xiao Peng, Satoshi Goto
2013	J	`jnl`	A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jiayi Zhu, Dajiang Zhou, Satoshi Goto
2013	B	`conf`	A combined SAO and de-blocking filter architecture for HEVC video decoder. ICIP Jiayi Zhu, Dajiang Zhou, Gang He, Satoshi Goto
2013	B	`conf`	A high-performance CABAC encoder architecture for HEVC and H.264/AVC. ICIP Jinjia Zhou, Dajiang Zhou, Wei Fei, Satoshi Goto
2013	—	`conf`	An FPGA-based 4K UHDTV H.264/AVC video decoder. ICME Workshops Yue Pan, Dajiang Zhou, Satoshi Goto
2013	—	`conf`	High-parallel performance-aware LDPC decoder IP core design for WiMAX. MWSCAS Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto
2013	—	`conf`	Lossless embedded compression using multi-mode DPCM & averaging prediction for HEVC-like video codec. EUSIPCO Li Guo, Dajiang Zhou, Satoshi Goto
2013	—	`conf`	Transform-based fast mode and depth decision algorithm for HEVC intra prediction. ASICON Gang He, Dajiang Zhou, Satoshi Goto
2012	J	`jnl`	A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiongxin Zhao, Xiao Peng, Zhixiang Chen, Dajiang Zhou, Satoshi Goto
2012	—	`conf`	A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder. EUSIPCO Gang He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto
2012	—	`conf`	A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. ISSCC Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto
2012	—	`conf`	A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC. VLSIC Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto
2012	A	`conf`	A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering. ICME Heming Sun, Dajiang Zhou, Satoshi Goto
2012	J	`jnl`	An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding. IEEE Trans. Multim. Xuena Bao, Dajiang Zhou, Peilin Liu, Satoshi Goto
2012	Misc	`conf`	An optimized MC interpolation architecture for HEVC. ICASSP Zhengyan Guo, Dajiang Zhou, Satoshi Goto
2012	J	`jnl`	DVB-T2 LDPC Decoder with Perfect Conflict Resolution. Inf. Media Technol. Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto
2012	J	`jnl`	DVB-T2 LDPC Decoder with Perfect Conflict Resolution. IPSJ Trans. Syst. LSI Des. Methodol. Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto
2012	—	`conf`	DVB-T2 LDPC decoder with perfect conflict resolution. VLSI-DAT Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto
2012	—	`conf`	De-blocking Filter Design for HEVC and H.264/AVC. PCM Muchen Li, Jinjia Zhou, Dajiang Zhou, Xiao Peng, Satoshi Goto
2012	B	`conf`	Interlaced asymmetric search range assignment for bidirectional motion estimation. ICIP Jinjia Zhou, Dajiang Zhou, Satoshi Goto
2011	—	`conf`	A 1 Gbin/s CABAC encoder for H.264/AVC. EUSIPCO Wei Fei, Dajiang Zhou, Satoshi Goto
2011	—	`conf`	A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS. A-SSCC Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto
2011	—	`conf`	A 16-65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications. EUSIPCO Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto
2011	J	`jnl`	A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. IEEE J. Solid State Circuits Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto
2011	J	`jnl`	A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder. IEICE Trans. Electron. Gang He, Dajiang Zhou, Jinjia Zhou, Tianruo Zhang, Satoshi Goto
2011	J	`jnl`	A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto
2011	J	`jnl`	A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xun He, Xin Jin, Minghui Wang, Dajiang Zhou, Satoshi Goto
2011	A	`conf`	A 98 GMACs/W 32-core vector processor in 65nm CMOS. ISLPED Xun He, Dajiang Zhou, Xin Jin, Satoshi Goto
2011	—	`conf`	A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. SiPS Qian Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto
2011	J	`jnl`	Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder. IEICE Trans. Electron. Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto
2011	—	`conf`	Ultra low power QC-LDPC decoder with high parallelism. SoCC Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto
2010	J	`jnl`	A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jinjia Zhou, Dajiang Zhou, Xun He, Satoshi Goto
2010	—	`conf`	A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding. PCM (2) Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto
2010	J	`jnl`	A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. Inf. Media Technol. Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto
2010	J	`jnl`	A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. IPSJ Trans. Syst. LSI Des. Methodol. Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto
2010	J	`jnl`	A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder. IEICE Trans. Electron. Xianmin Chen, Peilin Liu, Dajiang Zhou, Jiayi Zhu, Xingguang Pan, Satoshi Goto
2010	—	`conf`	A constant rate bandwidth reduction architecture with adaptive compression mode decision for video decoding. EUSIPCO Liu Song, Dajiang Zhou, Xin Jin, Satoshi Goto
2010	C	`conf`	A lossless frame recompression scheme for reducing DRAM power in video encoding. ISCAS Xuena Bao, Dajiang Zhou, Satoshi Goto
2010	C	`conf`	An adaptive bandwidth reduction scheme for video coding. ISCAS Liu Song, Dajiang Zhou, Xin Jin, Satoshi Goto, Peilin Liu
2010	A	`conf`	An advanced hierarchical motion estimation scheme with lossless frame recompression for ultra high definition video coding. ICME Xuena Bao, Dajiang Zhou, Peilin Liu, Satoshi Goto
2010	C	`conf`	An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards. ISCAS Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto
2010	J	`jnl`	High Profile Intra Prediction Architecture for UHD H.264 Decoder. Inf. Media Technol. Xun He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto
2010	J	`jnl`	High Profile Intra Prediction Architecture for UHD H.264 Decoder. IPSJ Trans. Syst. LSI Des. Methodol. Xun He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto
2010	C	`conf`	Intra prediction architecture for H.264/AVC QFHD encoder. PCS Gang He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto
2009	A	`conf`	A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications. ICME Jinjia Zhou, Dajiang Zhou, Hang Zhang, Yu Hong, Peilin Liu, Satoshi Goto
2009	J	`jnl`	A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Satoshi Goto
2009	J	`jnl`	An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Dajiang Zhou, Jinjia Zhou, Satoshi Goto
2009	C	`conf`	Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder. ISCAS Xianmin Chen, Peilin Liu, Jiayi Zhu, Dajiang Zhou, Satoshi Goto
2009	C	`conf`	Prioritized Reference Decision for Efficient Motion Vector Coding. ISCAS Dajiang Zhou, Jinjia Zhou, Satoshi Goto
2008	C	`conf`	An SDRAM controller optimized for high definition video coding application. ISCAS Jiayi Zhu, Peilin Liu, Dajiang Zhou
2007	C	`conf`	A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. ISCAS Dajiang Zhou, Peilin Liu