Daisuke Ikebuchi

14 papers A 1C 1Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2011 J jnl
A Leakage Efficient Data TLB Design for Embedded Processors.
IEICE Trans. Inf. Syst.
Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano
2011 J jnl
A Leakage Efficient Instruction TLB Design for Embedded Processors.
IEICE Trans. Inf. Syst.
Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano
2011 — conf
Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
FPT
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011 J jnl
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
IEEE Micro
Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011 J jnl
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
Inf. Media Technol.
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011 J jnl
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. Syst. LSI Des. Methodol.
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011 — conf
Geyser-2: The second prototype CPU with fine-grained run-time power gating.
ASP-DAC
Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
2011 A conf
On-chip detection methodology for break-even time of power gated function units.
ISLPED
Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
2011 J jnl
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2010 — conf
Adaptive power gating for function units in a microprocessor.
ISQED
Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2010 — conf
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
ASP-DAC
Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo
2010 — conf
Reducing instruction TLB's leakage power consumption for embedded processors.
Green Computing Conference
Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki
2010 — conf
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
NOCS
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2008 C conf
A fine-grain dynamic sleep control scheme in MIPS R3000.
ICCD
Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura