Daisuke Fujimoto

47 papers A* 2A 1C 2Journal 21Unranked 21
YearRankTypeTitle / Venue / Authors
2026 J jnl
Active Electromagnetic Side-Channel Analysis: Crossing Physical Security Boundaries through Impedance Variations.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Taiki Kitazawa, Lennert Wouters, Benedikt Gierlichs, Daisuke Fujimoto, Ingrid Verbauwhede, Yuichi Hayashi
2025 — conf
Amplifying Electromagnetic Leakage by Hardware Trojans Through Cable Geometry Manipulation.
HOST
Hayato Ide, Shohei Matsumoto, Taiki Kitazawa, Shugo Kaji, Daisuke Fujimoto, Takashi Kasuga, Yuichi Hayashi
2025 J jnl
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC.
ACM Trans. Reconfigurable Technol. Syst.
Tianyou Bao, Pengzhou He, Daisuke Fujimoto, Yuichi Hayashi, Jiafeng Xie
2025 J jnl
Capacitance Sensor-Based Board-Level PUF for Device Identification.
IEEE Access
Rikuo Haga, Ayaki Tachikake, Shugo Kaji, Daisuke Fujimoto, Yuichi Hayashi
2025 — conf
Current consumption model for more efficient side-channel tolerant design at FPGA design stage.
ASP-DAC
Daisuke Fujimoto, Yuichi Hayashi
2025 — conf
Detection of Hardware Trojans Using a Capacitance Sensor Focused on Parasitic Coupling Between Wires.
NewCAS
Rikuo Haga, Shugo Kaji, Daisuke Fujimoto, Yuichi Hayashi
2025 J jnl
Fault to Forge: Fault Assisted Forging Attacks on LESS Signature Scheme.
IACR Cryptol. ePrint Arch.
Puja Mondal, Suparna Kundu, Hikaru Nishiyama, Supriya Adhikary, Daisuke Fujimoto, Yuichi Hayashi, Angshuman Karmakar
2025 J jnl
Remote fault injection attack against cryptographic modules via intentional electromagnetic interference from an antenna.
J. Cryptogr. Eng.
Hikaru Nishiyama, Daisuke Fujimoto, Yuichi Hayashi
2024 — conf
Controlling Faulty Byte Outputs with IEMI against Cryptographic ICs.
EMC Compo
Hikaru Nishiyama, Daisuke Fujimoto, Yuichi Hayashi
2024 — conf
Current Consumption Modeling of Logic Cells Based on Measurements for Side-channel Attack Simulation.
EMC Compo
Daisuke Fujimoto, Taichi Sato, Yuichi Hayashi
2024 — conf
Fundamental Study on Detecting Hardware Trojans in Printed Circuit Boards Using Ring Oscillators.
EMC Compo
Koki Abe, Daisuke Fujimoto, Yuichi Hayashi
2024 J jnl
High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Junichi Sakamoto, Daisuke Fujimoto, Riku Anzai, Naoki Yoshida, Tsutomu Matsumoto
2023 — conf
Remote Fault Injection Attack against Cryptographic Modules via Intentional Electromagnetic Interference from an Antenna.
ASHES@CCS
Hikaru Nishiyama, Daisuke Fujimoto, Yuichi Hayashi
2022 J jnl
Constructing software countermeasures against instruction manipulation attacks: an approach based on vulnerability evaluation using fault simulator.
Clust. Comput.
Junichi Sakamoto, Shungo Hayashi, Daisuke Fujimoto, Tsutomu Matsumoto
2021 J jnl
Efficient Algorithms for Sign Detection in RNS Using Approximate Reciprocals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Kawamura, Yuichi Komano, Hideo Shimizu, Saki Osuka, Daisuke Fujimoto, Yu-ichi Hayashi, Kentaro Imafuku
2020 — conf
Comparison of Pearson correlation coefficient and distance correlation in Correlation Power Analysis on Digital Multiplier.
MIPRO
Jurica Kundrata, Daisuke Fujimoto, Yu-ichi Hayashi, Adrijan Baric
2020 C conf
How to Code Data Integrity Verification Secure Against Single-Spot-Laser-Induced Instruction Manipulation Attacks.
AICCSA
Junichi Sakamoto, Shungo Hayashi, Daisuke Fujimoto, Tsutomu Matsumoto
2020 J jnl
Laser-Induced Controllable Instruction Replacement Fault Attack.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto
2019 C conf
Design Considerations for EM Pulse Fault Injection.
CARDIS
Arthur Beckers, Masahiro Kinugawa, Yu-ichi Hayashi, Daisuke Fujimoto, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede
2019 J jnl
Electromagnetic Information Extortion from Electronic Devices Using Interceptor and Its Countermeasure.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Masahiro Kinugawa, Daisuke Fujimoto, Yu-ichi Hayashi
2019 J jnl
Fundamental Study on the Effects of Connector Torque Value on the Change of Inductance at the Contact Boundary.
IEICE Trans. Electron.
Daisuke Fujimoto, Takashi Narimatsu, Yu-ichi Hayashi
2019 — conf
Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier.
AsianHOST
Junichi Sakamoto, Yusuke Nagahama, Daisuke Fujimoto, Yota Okuaki, Tsutomu Matsumoto
2018 J jnl
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs.
IEEE Trans. Circuits Syst. II Express Briefs
Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto
2017 J jnl
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks.
J. Cryptol.
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki
2017 J jnl
Protecting cryptographic integrated circuits with side-channel information.
IEICE Electron. Express
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama
2016 J jnl
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version).
IACR Cryptol. ePrint Arch.
Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger
2016 — conf
How to design hardware prime field multipliers for bilinear pairing.
ISOCC
Daisuke Fujimoto, Yusuke Nagahama, Tsutomu Matsumoto
2016 — conf
Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits.
AsianHOST
Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto
2015 J jnl
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan.
IEEE J. Solid State Circuits
Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
2015 — conf
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor.
ASP-DAC
Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
2015 J jnl
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.
IEEE Trans. Very Large Scale Integr. Syst.
Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki
2015 — conf
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement.
ASP-DAC
Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger
2015 A* conf
EM attack sensor: concept, circuit, and design-automation methodology.
DAC
Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki
2014 — conf
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
ISSCC
Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
2014 — conf
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor.
VLSIC
Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
2014 — conf
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor.
A-SSCC
Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata
2014 J jnl
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor.
IACR Cryptol. ePrint Arch.
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
2014 A conf
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor.
CHES
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
2014 — conf
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips.
ATS
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura
2014 — conf
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.
ES4CPS@DATE
Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata
2014 J jnl
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron.
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
2014 — conf
Side-channel leakage on silicon substrate of CMOS cryptographic chip.
HOST
Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger
2013 J jnl
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
2011 — conf
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.
HOST
Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh
2010 J jnl
An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology.
IEICE Trans. Electron.
Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata
2009 — conf
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology.
CICC
Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata
2003 A* conf
Improvement of passive elements for wearable haptic displays.
ICRA
Sadao Kawamura, Katsuya Kanaoka, Yuichiro Nakayama, Jinwoo Jeon, Daisuke Fujimoto