Daisaburo Takashima

29 papers Journal 22Unranked 7

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	A 7T-SRAM With Data-Write Technique by Capacitive Coupling. IEEE J. Solid State Circuits Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino
2015	—	`conf`	A 7T-SRAM with data-write technique by capacitive coupling. A-SSCC Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino
2015	J	`jnl`	Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs. IEEE J. Solid State Circuits Ryu Ogiwara, Daisaburo Takashima, Sumiko M. Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga
2012	J	`jnl`	An Embedded DRAM Technology for High-Performance NAND Flash Memories. IEEE J. Solid State Circuits Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii
2012	—	`conf`	Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee. ISSCC Joo-Sun Choi, Daisaburo Takashima
2011	J	`jnl`	A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell. IEEE J. Solid State Circuits Daisaburo Takashima, Yasushi Nagadomi, Tohru Ozaki
2011	J	`jnl`	A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance. IEEE J. Solid State Circuits Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii
2011	J	`jnl`	A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. IEEE J. Solid State Circuits Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama
2011	—	`conf`	An embedded DRAM technology for high-performance NAND flash memories. ISSCC Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii
2011	—	`conf`	Future system and memory architectures: Transformations by technology and applications. ISSCC Nicky Lu, Leland Chang, Daisaburo Takashima
2010	J	`jnl`	A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. IEEE J. Solid State Circuits Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama
2010	J	`jnl`	A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. IEEE Trans. Very Large Scale Integr. Syst. Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii
2010	—	`conf`	A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. ISSCC Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama
2009	—	`conf`	A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. ISSCC Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama
2006	—	`conf`	A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. ISSCC Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii
2003	J	`jnl`	A 32-Mb chain FeRAM with segment/stitch array architecture. IEEE J. Solid State Circuits Shinichiro Shiratake, Tadashi Miyakawa, Yoshiaki Takeuchi, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Kohei Oikawa, Tohru Ozaki, Iwao Kunishima, Koji Yamakawa, Shigeki Sugimoto, Daisaburo Takashima, Hans-Oliver Joachim, Norbert Rehm, Joerg Wohlfahrt, Nicolas Nagel, Gerhard Beitel, Michael Jacob, Thomas Roehr
2002	J	`jnl`	A cell transistor scalable DRAM array architecture. IEEE J. Solid State Circuits Daisaburo Takashima, Hiroaki Nakano
2001	J	`jnl`	A 76-mm IEEE J. Solid State Circuits Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki
1999	J	`jnl`	A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. IEEE J. Solid State Circuits Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka
1998	J	`jnl`	High-density chain ferroelectric random access memory (chain FRAM). IEEE J. Solid State Circuits Daisaburo Takashima, Iwao Kunishima
1998	J	`jnl`	Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's. IEEE J. Solid State Circuits Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi
1997	J	`jnl`	A novel power-off mode for a battery-backup DRAM. IEEE J. Solid State Circuits Daisaburo Takashima, Yukihito Oowaki
1994	J	`jnl`	Open/folded bit-line arrangement for ultra-high-density DRAM's. IEEE J. Solid State Circuits Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi
1994	J	`jnl`	Standby/active mode logic for sub-1-V operating ULSI memory. IEEE J. Solid State Circuits Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango
1993	J	`jnl`	An experimental DRAM with a NAND-structured cell. IEEE J. Solid State Circuits Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Masako Ohta, Shinichiro Shiratake, Takeshi Hamamoto, Takashi Yamada, Masami Aoki, Shigeru Ishibashi, Yukihito Oowaki, Shigeyoshi Watanabe, Fujio Masuoka
1993	J	`jnl`	Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs. IEEE J. Solid State Circuits Daisaburo Takashima, Shigeyoshi Watanabe, Tsuneaki Fuse, Kazumasa Sunouchi, Takahiko Hara
1992	J	`jnl`	Word-line architecture for highly reliable 64-Mb DRAM. IEEE J. Solid State Circuits Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi
1991	J	`jnl`	A 33-ns 64-Mb DRAM. IEEE J. Solid State Circuits Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka
1990	J	`jnl`	The stabilized reference-line (SRL) technique for scaled DRAMs. IEEE J. Solid State Circuits Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka