Dai Yamamoto

28 papers A 2B 2C 4Misc 1Journal 13Unranked 6
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Chameleon Hash-based Method for Proving Execution of Business Processes.
J. Inf. Process.
Tadanobu Tsunoda, Kazuaki Nimura, Dai Yamamoto, Kouichi Yasaki, Rikuhiro Kojima, Yosuke Nakamura
2021 J jnl
A New Schnorr Multi-Signatures to Support Both Multiple Messages Signing and Key Aggregation.
J. Inf. Process.
Rikuhiro Kojima, Dai Yamamoto, Takeshi Shimoyama, Kouichi Yasaki, Kazuaki Nimura
2021 J jnl
Novel Deception Techniques for Malware Detection on Industrial Control Systems.
J. Inf. Process.
Takanori Machida, Dai Yamamoto, Yuki Unno, Hisashi Kojima
2020 — conf
A Novel Scheme of Schnorr Multi-signatures for Multiple Messages with Key Aggregation.
BWCCA
Rikuhiro Kojima, Dai Yamamoto, Takeshi Shimoyama, Kouichi Yasaki, Kazuaki Nimura
2020 J jnl
Novel Deception Techniques for Malware Detection on Industrial Control Systems.
IACR Cryptol. ePrint Arch.
Takanori Machida, Dai Yamamoto, Yuki Unno, Hisashi Kojima
2018 — conf
A Secure Framework for User-Key Provisioning to SGX Enclaves.
NBiS
Takanori Machida, Dai Yamamoto, Ikuya Morikawa, Hirotaka Kokubo, Hisashi Kojima
2016 J jnl
ASIC implementation of random number generators using SR latches and its evaluation.
EURASIP J. Inf. Secur.
Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto
2016 — conf
Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs.
CANDAR
Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto
2016 — conf
Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.
TrustED@CCS
Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto
2016 J jnl
Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto
2015 J jnl
A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs.
J. Cryptogr. Eng.
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
2015 — conf
Implementation of double arbiter PUF and its performance evaluation on FPGA.
ASP-DAC
Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama
2014 C conf
A New Mode of Operation for Arbiter PUF to Improve Uniqueness on FPGA.
FedCSIS
Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama
2014 Misc conf
A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering.
IWSEC
Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
2014 J jnl
Dynamic Behavior of RS latches using FIB processing and probe connection.
IACR Cryptol. ePrint Arch.
Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto
2014 C conf
Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis.
FedCSIS
Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
2013 C conf
Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches.
CARDIS
Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
2013 J jnl
Variety enhancement of PUF responses using the locations of random outputting RS latches.
J. Cryptogr. Eng.
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh
2012 — conf
Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs.
SPACE
Dai Yamamoto, Gabriel Hospodar, Roel Maes, Ingrid Verbauwhede
2011 J jnl
Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Dai Yamamoto, Kouichi Itoh, Jun Yajima
2011 A conf
Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches.
CHES
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Takao Ochiai, Masahiko Takenaka, Kouichi Itoh
2010 C conf
A Very Compact Hardware Implementation of the KASUMI Block Cipher.
WISTP
Dai Yamamoto, Kouichi Itoh, Jun Yajima
2010 J jnl
Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Dai Yamamoto, Jun Yajima, Kouichi Itoh
2009 J jnl
Collision-Based Power Attack for RSA with Small Public Exponent.
IEICE Trans. Inf. Syst.
Kouichi Itoh, Dai Yamamoto, Jun Yajima, Wakaha Ogata
2008 A conf
A Very Compact Hardware Implementation of the MISTY1 Block Cipher.
CHES
Dai Yamamoto, Jun Yajima, Kouichi Itoh
2008 J jnl
Design and Experimental Evaluation of a Scheme for Maximal Improvement of End-to-End QoS in Heterogeneous IP Networks.
IEICE Trans. Commun.
Dai Yamamoto, Hideki Tode, Toshihiro Masaki, Koso Murakami
2007 B conf
Design and Empirical Evaluation of Control Scheme for End-to-End Delay Stabilization and Packet Loss Improvement in Broadband IP Network.
ICCCN
Dai Yamamoto, Hideki Tode, Toshihiro Masaki, Koso Murakami
2005 B conf
A Method for Guaranteeing End-to-End Delay by Mutual Cooperation between IP Routers.
LCN
Dai Yamamoto, Rie Fujita, Hideki Tode, Koso Murakami, Toshihiro Masaki