Dafine Ravelosona

23 papers A 2C 2Journal 10Unranked 9
YearRankTypeTitle / Venue / Authors
2021 J jnl
Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations.
CoRR
Xing Chen, Flavio Abreu Araujo, Mathieu Riou, Jacob Torrejon, Dafine Ravelosona, Wang Kang, Weisheng Zhao, Julie Grollier, Damien Querlioz
2019 J jnl
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guanda Wang, Yue Zhang, Beibei Zhang, Bi Wu, Jiang Nan, Xueying Zhang, Zhizhong Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2016 J jnl
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
2015 A conf
From device to system: cross-layer design exploration of racetrack memory.
DATE
Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang
2015 C conf
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
ISCAS
Yue Zhang, Chao Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
2015 J jnl
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
ACM J. Emerg. Technol. Comput. Syst.
Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao
2015 J jnl
Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wang Kang, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 — conf
An overview of spin-based integrated circuits.
ASP-DAC
Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 — conf
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
NANOARCH
Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona
2014 J jnl
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput.
Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert
2014 — conf
One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
NVMSA
Wang Kang, Weisheng Zhao, Lun Yang, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona
2014 A conf
Spintronics for low-power computing.
DATE
Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 J jnl
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert
2013 J jnl
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab.
Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona
2013 — conf
Analytical study of complementary memristive synchronous logic gates.
NANOARCH
Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao
2013 — conf
Emerging hybrid logic circuits based on non-volatile magnetic memories.
NEWCAS
Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona
2013 J jnl
Magnetic Adder Based on Racetrack Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein, Yue Zhang, Dafine Ravelosona, Claude Chappert
2013 C conf
Spin-electronics based logic fabrics.
VLSI-SoC
Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert
2013 — conf
Synchronous full-adder based on complementary resistive switching memory cells.
NEWCAS
Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012 — conf
Crossbar architecture based on 2R complementary resistive switching memory cell.
NANOARCH
Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012 J jnl
Failure and reliability analysis of STT-MRAM.
Microelectron. Reliab.
Weisheng Zhao, Yue Zhang, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer
2011 — conf
Design of MRAM based logic circuits and its applications.
ACM Great Lakes Symposium on VLSI
Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitorio Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert
2011 — conf
High Performance SoC Design Using Magnetic Logic and Memory.
VLSI-SoC (Selected Papers)
Weisheng Zhao, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert