Daeyeal Lee

15 papers A 1C 2Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2022 — —
Logical Reasoning Techniques for VLSI Applications
Daeyeal Lee
2022 J jnl
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin
2022 J jnl
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform.
IEEE Access
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin
2022 J jnl
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo
2022 J jnl
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing.
ACM Trans. Archit. Code Optim.
Daeyeal Lee, Bill Lin, Chung-Kuan Cheng
2021 C conf
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation.
ICCD
Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo
2021 J jnl
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park
2021 J jnl
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC.
IEEE Embed. Syst. Lett.
Daeyeal Lee, Bill Lin, Chung-Kuan Cheng
2021 J jnl
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2020 A conf
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT.
ICCAD
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park
2020 J jnl
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dongwon Park, Daeyeal Lee, Ilgweon Kang, Chester Holtz, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2020 — conf
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm.
ASP-DAC
Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2020 C conf
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility.
ISCAS
Chung-Kuan Cheng, Daeyeal Lee, Dongwon Park
2012 — conf
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology.
ISSCC
Daeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byungjun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, AnSoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, HooSung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun
2006 — conf
An Effective Test Pattern Generation for Testing Signal Integrity.
ATS
YongJoon Kim, Myung-Hoon Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang