Dae Hyun Kwon

16 papers Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2021 J jnl
A Low-Power 28-Gb/s PAM-4MZM Driver With Level Pre-Distortion.
IEEE Trans. Circuits Syst. II Express Briefs
Minkyu Kim, Dae Hyun Kwon, Daewon Rho, Woo-Young Choi
2020 J jnl
A Low-Power 40-Gb/s Pre-Emphasis PAM-4 Transmitter With Toggling Serializers.
IEEE Trans. Circuits Syst. II Express Briefs
Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi
2019 J jnl
A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi
2018 — conf
A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS.
ISSCC
Qing Liu, Dae Hyun Kwon, Quang-Diep Bui, Jeong-Hyun Choi, Jaehun Lee, Sanghyun Baek, Seungchan Heo, Thomas Byunghak Cho
2017 — conf
13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS.
ISSCC
Venumadhav Bhagavatula, Dae Hyun Kwon, Jaehun Lee, Quang-Diep Bui, Jeong-Hyun Choi, Siuchuang-Ivan Lu, Sang Won Son
2016 — conf
A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector.
APCCAS
Ki-Hyun Pyun, Dae Hyun Kwon, Woo-Young Choi
2016 — conf
A 5-8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization.
A-SSCC
Sung-Geun Kim, Tongsung Kim, Dae Hyun Kwon, Woo-Young Choi
2016 J jnl
A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS.
IEEE J. Solid State Circuits
Siddharth Seth, Dae Hyun Kwon, Sriramkumar Venugopalan, Sang Won Son, Yongrong Zuo, Venumadhav Bhagavatula, Jaehyun Lim, Dongjin Oh, Thomas Byunghak Cho
2016 J jnl
A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO.
IEEE Trans. Circuits Syst. II Express Briefs
Sung-Geun Kim, Jinsoo Rhim, Dae Hyun Kwon, Min-Hyeong Kim, Woo-Young Choi
2015 J jnl
A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dae Hyun Kwon, Young-Seok Park, Woo-Young Choi
2014 — conf
A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation.
CICC
Joung-Wook Moon, Sung-Geun Kim, Dae Hyun Kwon, Woo-Young Choi
2010 J jnl
A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling.
IEEE J. Solid State Circuits
Richard Tseng, Hao Li, Dae Hyun Kwon, Yun Chiu, Ada S. Y. Poon
2010 J jnl
Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier.
IEEE J. Solid State Circuits
Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu
2010 — —
Digitally enhanced CMOS RF transmitter with integrated power amplifier
Dae Hyun Kwon
2009 J jnl
A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation.
IEEE J. Sel. Top. Signal Process.
Hao Li, Dae Hyun Kwon, Deming Chen, Yun Chiu
2009 — conf
CMOS RF transmitter with integrated power amplifier utilizing digital equalization.
CICC
Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu