Dae Hyun Kim

44 papers A* 1A 4C 2Journal 21Unranked 16
YearRankTypeTitle / Venue / Authors
2024 J jnl
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing.
ACM Trans. Design Autom. Electr. Syst.
Monzurul Islam Dewan, Sheng-En David Lin, Dae Hyun Kim
2022 A* conf
Bayesian Optimization over Permutation Spaces.
AAAI
Aryan Deshwal, Syrine Belakaria, Janardhan Rao Doppa, Dae Hyun Kim
2022 J jnl
Design Automation Algorithms for the NP-Separate VLSI Design Methodology.
ACM Trans. Design Autom. Electr. Syst.
Monzurul Islam Dewan, Dae Hyun Kim
2021 J jnl
Bayesian Optimization over Permutation Spaces.
CoRR
Aryan Deshwal, Syrine Belakaria, Janardhan Rao Doppa, Dae Hyun Kim
2021 J jnl
HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration.
ACM Trans. Design Autom. Electr. Syst.
Aqeeb Iqbal Arka, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande
2020 J jnl
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sheng-En David Lin, Dae Hyun Kim
2020 J jnl
HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration.
CoRR
Aqeeb Iqbal Arka, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande
2020 J jnl
Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration.
IEEE Trans. Very Large Scale Integr. Syst.
Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Partha Pratim Pande
2020 J jnl
NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Monzurul Islam Dewan, Dae Hyun Kim
2020 A conf
Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips.
DATE
Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande
2019 — conf
A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design.
ISQED
Shantonu Das, Dae Hyun Kim
2019 — conf
Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing.
ISPD
Sheng-En David Lin, Dae Hyun Kim
2019 A conf
Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers.
DATE
Jihee Seo, Dae Hyun Kim
2019 C conf
High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding.
ARITH
Jihee Seo, Dae Hyun Kim
2019 J jnl
Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures.
CoRR
Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Partha Pratim Pande
2019 — conf
Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits.
ISQED
Sheng-En David Lin, Dae Hyun Kim
2019 J jnl
Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs.
IEEE Trans. Emerg. Top. Comput.
Sheng-En David Lin, Dae Hyun Kim
2018 J jnl
Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Inki Hong, Dae Hyun Kim
2018 — conf
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid.
ISPD
Sheng-En David Lin, Dae Hyun Kim
2018 J jnl
Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach.
ACM J. Emerg. Technol. Comput. Syst.
Dongjin Lee, Sourav Das, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande
2018 J jnl
Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sheng-En David Lin, Dae Hyun Kim
2017 — conf
A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits.
ISQED
Yiting Chen, Dae Hyun Kim
2016 — conf
Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs.
ISQED
Sheng-En David Lin, Partha Pratim Pande, Dae Hyun Kim
2015 J jnl
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools.
IEEE Des. Test
Dae Hyun Kim, Sung Kyu Lim
2015 J jnl
Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities.
IEEE Des. Test
Dae Hyun Kim, Sung Kyu Lim
2015 — conf
Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures.
ACM Great Lakes Symposium on VLSI
Sourav Das, Dongjin Lee, Dae Hyun Kim, Partha Pratim Pande
2014 J jnl
Backend Dielectric Reliability Full Chip Simulator.
IEEE Trans. Very Large Scale Integr. Syst.
Muhammad Muqarrab Bashir, Chang-Chih Chen, Linda Milor, Dae Hyun Kim, Sung Kyu Lim
2013 — conf
Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs.
ASP-DAC
Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim
2013 J jnl
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout.
IEEE Trans. Very Large Scale Integr. Syst.
Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
2012 — conf
3D-MAPS: 3D Massively parallel processor with stacked memory.
ISSCC
Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2012 J jnl
Backend dielectric reliability simulator for microprocessor system.
Microelectron. Reliab.
Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, Linda Milor
2012 — conf
Block-level 3D IC design with through-silicon-via planning.
ASP-DAC
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
2012 J jnl
Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Dae Hyun Kim, Sung Kyu Lim
2012 — conf
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices.
ISQED
Kaiyuan Yang, Dae Hyun Kim, Sung Kyu Lim
2011 — conf
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.
ISQED
Taigon Song, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon
2011 J jnl
Impact of irregular geometries on low-k dielectric breakdown.
Microelectron. Reliab.
Muhammad Bashir, Linda Milor, Dae Hyun Kim, Sung Kyu Lim
2011 — conf
TSV density-driven global placement for 3D stacked ICs.
ISOCC
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
2010 — conf
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.
CICC
Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2010 A conf
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system.
ICCAD
Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay
2010 J jnl
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown.
Microelectron. Reliab.
Muhammad Bashir, Linda S. Milor, Dae Hyun Kim, Sung Kyu Lim
2009 A conf
A study of Through-Silicon-Via impact on the 3D stacked IC layout.
ICCAD
Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
2009 — conf
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.
SLIP
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
2008 — conf
Bus-aware microarchitectural floorplanning.
ASP-DAC
Dae Hyun Kim, Sung Kyu Lim
2008 C conf
Global bus route optimization with application to microarchitectural design exploration.
ICCD
Dae Hyun Kim, Sung Kyu Lim