Dadian Zhou - RankMe

13 papers C 1Journal 9Unranked 3

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Look-Up Table-Based Digital Calibration for the Correction of Pipeline Analog-to-Digital Converter Non-Idealities. IEEE Access Shangfeng Qiu, Dadian Zhou, Martin Kinyua, Jose Silva-Martinez
2024	J	`jnl`	Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Amr Walid, Dadian Zhou, Jose Silva-Martinez
2021	J	`jnl`	Recent Advances on Linear Low-Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs José Silva-Martínez, Xiaosen Liu, Dadian Zhou
2020	J	`jnl`	A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier. IEEE Trans. Circuits Syst. Chulhyun Park, Tao Chen, Kyoohyun Noh, Dadian Zhou, Suraj Prakash, Mohammadhossein Naderi Alizadeh, Aydin I. Karsilayan, Degang Chen, Randall L. Geiger, José Silva-Martínez
2020	J	`jnl`	A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator. IEEE J. Solid State Circuits Dadian Zhou, Junning Jiang, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2020	J	`jnl`	A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test. IEEE Trans. Instrum. Meas. Tao Chen, Chulhyun Park, Hao Meng, Dadian Zhou, José Silva-Martínez, Randall L. Geiger, Degang Chen
2019	J	`jnl`	A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2018	J	`jnl`	A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. IEEE J. Solid State Circuits Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2018	J	`jnl`	A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez
2017	C	`conf`	A 13bit 200MS/S pipeline ADC with current-mode MDACs. ISCAS Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez
2017	—	`conf`	A 200MSPS time-interleaved 12-bit ADC system with digital calibration. MWSCAS Aditya Bommireddipalli, Dadian Zhou, Claudio Talarico, José Silva-Martínez, Aydin I. Karsilayan
2016	—	`conf`	A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration. SoCC Dadian Zhou, Claudio Talarico, José Silva-Martínez
2012	—	`conf`	Brain Storm Optimization Algorithm with Modified Step-Size and Individual Generation. ICSI (1) Dadian Zhou, Yuhui Shi, Shi Cheng