D. Michael Miller

103 papers A* 2A 4B 1C 13Journal 38Unranked 40

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	On the Contributions to Multiple-Valued Logic by Prof. Kenneth C. Smith. ISMVL D. Michael Miller
2021	—	`conf`	Descending Order Transformation-based Synthesis of MVL Reversible Circuits. ISMVL D. Michael Miller, Gerhard W. Dueck
2021	J	`jnl`	Function translations and search-based transformation for MVL reversible circuit synthesis. Sci. Comput. Program. D. Michael Miller, Gerhard W. Dueck
2020	J	`jnl`	A Spectral Algorithm for 3-valued Function Equivalence Classification. J. Multiple Valued Log. Soft Comput. D. Michael Miller, Mathias Soeken
2020	—	`conf`	Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms. ISMVL Kaitlin N. Smith, Mitchell A. Thornton, D. Michael Miller
2020	C	`conf`	Search-Based Transformation Synthesis for 3-Valued Reversible Circuits. RC D. Michael Miller, Gerhard W. Dueck
2019	—	`conf`	A Hybrid Method for Spectral Translation Equivalent Boolean Functions. PACRIM Mathias Soeken, Eleonora Testa, D. Michael Miller
2018	—	`conf`	A Spectral Algorithm for Ternary Function Classification. ISMVL D. Michael Miller, Mathias Soeken
2016	C	`conf`	A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC Mathias Soeken, Gerhard W. Dueck, D. Michael Miller
2016	C	`conf`	An extension of transformation-based reversible and quantum circuit synthesis. ISCAS Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller
2016	J	`jnl`	Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2016	J	`jnl`	QMDDs: Efficient Quantum Function Representation and Manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
2016	J	`jnl`	Using SPIN to Check Simulink Stateflow Models. Int. J. Networked Distributed Comput. Chikatoshi Yamada, D. Michael Miller
2016	J	`jnl`	Using SPIN to Check Simulink Stateflow Models. Int. J. Networked Distributed Comput. Chikatoshi Yamada, D. Michael Miller
2015	J	`jnl`	Self-Inverse Functions and Palindromic Circuits. CoRR Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
2015	—	`conf`	Using QMDD in Numerical Methods for Solving Linear Differential Equations via Walsh Functions. ISMVL Radomir S. Stankovic, D. Michael Miller
2015	—	`conf`	Using SPIN to Check Nondeterministic Simulink Stateflow Models. ISMVL Chikatoshi Yamada, D. Michael Miller
2015	C	`conf`	Using SPIN to check Simulink Stateflow models. ICIS Chikatoshi Yamada, D. Michael Miller
2014	J	`jnl`	Embedding of Large Boolean Functions for Reversible Logic. CoRR Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2014	C	`conf`	Mapping NCV Circuits to Optimized Clifford+T Circuits. RC D. Michael Miller, Mathias Soeken, Rolf Drechsler
2014	J	`jnl`	Reversible, Information-Preserving Logic and Its Application. J. Multiple Valued Log. Soft Comput. Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
2014	J	`jnl`	Trading off circuit lines and gate costs in the synthesis of reversible logic. Integr. Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
2013	J	`jnl`	Clarification on the Mapping of Reversible Circuits to the NCV-v1 Library. CoRR Zahra Sasanian, Robert Wille, D. Michael Miller
2013	J	`jnl`	On quantum circuits employing roots of the Pauli matrices. CoRR Mathias Soeken, D. Michael Miller, Rolf Drechsler
2013	C	`ed.`	Reversible Computation - 5th International Conference, RC 2013, Victoria, BC, Canada, July 4-5, 2013. Proceedings RC Gerhard W. Dueck, D. Michael Miller
2012	—	`ed.`	42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012, Victoria, BC, Canada, May 14-16, 2012 ISMVL D. Michael Miller, Vincent C. Gaudet
2012	J	`jnl`	Equivalence Checking of Reversible Circuits. J. Multiple Valued Log. Soft Comput. Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2012	J	`jnl`	High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? J. Multiple Valued Log. Soft Comput. Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski
2012	J	`jnl`	Mapping a Multiple-control Toffoli Gate Cascade to an Elementary Quantum Gate Circuit. J. Multiple Valued Log. Soft Comput. Zahra Sasanian, D. Michael Miller
2012	—	`conf`	Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
2012	A*	`conf`	Realizing reversible circuits using a new class of quantum gates. DAC Zahra Sasanian, Robert Wille, D. Michael Miller
2012	—	`conf`	Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries. ISED D. Michael Miller, Zahra Sasanian
2012	J	`jnl`	Reducing Reversible Circuit Cost by Adding Lines. J. Multiple Valued Log. Soft Comput. D. Michael Miller, Robert Wille, Rolf Drechsler
2012	C	`conf`	Reversible and Quantum Circuit Optimization: A Functional Approach. RC Zahra Sasanian, D. Michael Miller
2012	J	`jnl`	Synthesis of Semi-Classical Quantum Circuits. J. Multiple Valued Log. Soft Comput. Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
2011	—	`conf`	Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates. ISMVL D. Michael Miller, Robert Wille, Zahra Sasanian
2011	—	`conf`	Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. ISMVL Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
2011	C	`conf`	Transforming MCT Circuits to NCVW Circuits. RC Zahra Sasanian, D. Michael Miller
2010	—	`conf`	Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups. ISMVL Stanislav Stankovic, Jaakko Astola, D. Michael Miller, Radomir S. Stankovic
2010	—	`conf`	Reducing Reversible Circuit Cost by Adding Lines. ISMVL D. Michael Miller, Robert Wille, Rolf Drechsler
2009	—	`conf`	A Heterogeneous Decision Diagram Package. EUROCAST D. Michael Miller, Radomir S. Stankovic
2009	—	`conf`	Equivalence Checking of Reversible Circuits. ISMVL Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2009	—	`conf`	Equivalence Checking of Reversible Circuits. MBMV Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2009	J	`jnl`	Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics. J. Multiple Valued Log. Soft Comput. David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller
2009	C	`conf`	Synthesizing Reversible Circuits for Irreversible Functions. DSD D. Michael Miller, Robert Wille, Gerhard W. Dueck
2008	C	`conf`	An efficient verification of quantum circuits under a practical restriction. CIT Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
2008	J	`jnl`	DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
2008	—	`book`	Multiple Valued Logic - Concepts and Representations. D. Michael Miller, Mitchell Aaron Thornton
2008	—	`conf`	On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. ISMVL David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller
2008	A	`conf`	Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. DATE David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller
2008	J	`jnl`	Quantum Circuit Simplification and Level Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne
2008	—	`conf`	Quantum Logic Implementation of Unary Arithmetic Operations. ISMVL Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller
2007	J	`jnl`	Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits. IET Comput. Digit. Tech. Dmitri Maslov, D. Michael Miller
2007	—	`book`	Multiple Valued Logic: Concepts and Representations Multiple Valued Logic D. Michael Miller, Mitchell A. Thornton
2007	J	`jnl`	QMDD Minimization Using Sifting for Variable Reordering. J. Multiple Valued Log. Soft Comput. D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton
2007	J	`jnl`	Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2007	—	`conf`	Variable Reordering and Sifting for QMDD. ISMVL D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton
2006	B	`conf`	A Decision Diagram Package for Reversible and Quantum Circuit Simulation. IEEE Congress on Evolutionary Computation D. Michael Miller, Mitchell A. Thornton, David Goodman
2006	—	`conf`	QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. ISMVL D. Michael Miller, Mitchell A. Thornton
2006	J	`jnl`	Synthesis of Quantum Multiple-Valued Circuits. J. Multiple Valued Log. Soft Comput. D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
2005	A	`conf`	Quantum Circuit Simplification Using Templates. DATE Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck
2005	J	`jnl`	Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. Very Large Scale Integr. Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2005	J	`jnl`	Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2004	—	`conf`	A Synthesis Method for MVL Reversible Logi. ISMVL D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov
2004	J	`jnl`	Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs. J. Multiple Valued Log. Soft Comput. Mitchell A. Thornton, D. Michael Miller
2004	—	`ed.`	Proceedings of the 3rd IEEE International Conference on Cognitive Informatics (ICCI 2004), 16-17 August 2004, Victoria, Canada IEEE ICCI Christine W. Chan, Witold Kinsner, Yingxu Wang, D. Michael Miller
2003	A*	`conf`	A transformation based algorithm for reversible logic synthesis. DAC D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
2003	—	`conf`	Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL D. Michael Miller, Rolf Drechsler
2003	A	`conf`	Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2003	J	`jnl`	Introduction: Special Issue in Recognition of Kenneth C. Smith. J. Multiple Valued Log. Soft Comput. Ali Sheikholeslami, D. Michael Miller
2003	—	`conf`	On the Size of Multiple-Valued Decision Diagrams. ISMVL D. Michael Miller, Gerhard W. Dueck
2003	—	`conf`	Simplification of Toffoli Networks via Templates. SBCCI Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2002	—	`conf`	Chrestenson Spectrum Computation Using Cayley Color Graphs. ISMVL Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend
2002	—	`conf`	Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
2002	—	`conf`	Multi-Output Timed Shannon Circuits. ISVLSI Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
2002	—	`conf`	On the Construction of Multiple-Valued Decision Diagrams. ISMVL D. Michael Miller, Rolf Drechsler
2001	—	`book`	Spectral techniques in VLSI CAD. Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller
2000	—	`conf`	Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. ISMVL Yasunori Nagata, D. Michael Miller, Masao Mukaidono
2000	A	`conf`	TOP: An Algorithm for Three-Level Optimization of PLDs. DATE Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio
1999	—	`conf`	B-ternary Logic Based Asynchronous Micropipeline. ISMVL Yasunori Nagata, D. Michael Miller, Masao Mukaidono
1998	J	`jnl`	An improved method for computing a generalized spectral coefficient. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. D. Michael Miller
1998	—	`conf`	Implementing a Multiple-Valued Decision Diagram Package. ISMVL D. Michael Miller, Rolf Drechsler
1998	—	`conf`	Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. ISMVL Yasunori Nagata, D. Michael Miller, Masao Mukaidono
1996	—	`conf`	A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. ISMVL Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller
1996	—	`conf`	A spectral method for Boolean function matching. ED&TC D. Michael Miller
1996	—	`conf`	Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. ISMVL D. Michael Miller, Noriaki Muranaka
1996	J	`jnl`	Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shujian Zhang, D. Michael Miller, Jon C. Muzio
1995	J	`jnl`	Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. J. Electron. Test. Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller
1994	—	`conf`	Spectral Transformation of Multiple-Valued Decision Diagrams. ISMVL D. Michael Miller
1994	C	`conf`	Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. ISCAS Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller
1993	—	`conf`	Decimal Addition and Subtraction Units Using the ISMVL Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller
1993	—	`conf`	Multiple-Valued Logic Design Tools. ISMVL D. Michael Miller
1992	—	`conf`	Autocorrelation Techniques for Multi-Bit Decoder PLAs. ISMVL Randal Tomczuk, D. Michael Miller
1992	C	`conf`	BIST Generators for Sequential Faults. ICCD Shujian Zhang, Rod Byrne, D. Michael Miller
1992	J	`jnl`	The OR-k method for on-line checking of programmable logic arrays. J. Electron. Test. D. M. Marcynuk, D. Michael Miller
1990	C	`conf`	Estimating aliasing in CA and LFSR based signature registers. ICCD D. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod
1990	—	`conf`	RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL Gerhard W. Dueck, D. Michael Miller
1990	J	`jnl`	The analysis of one-dimensional linear cellular automata and their aliasing properties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller
1989	J	`jnl`	Cellular automata-based pseudorandom number generators for built-in self-test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. Michael Miller, Howard C. Card
1984	J	`jnl`	Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks. IEEE Trans. Computers D. Michael Miller, Jon C. Muzio
1983	J	`jnl`	Spectral Fault Signatures for Internally Unate Combinational Networks. IEEE Trans. Computers D. Michael Miller, Jon C. Muzio
1980	J	`jnl`	A class of two-place three-valued unary generators. Notre Dame J. Formal Log. D. Michael Miller, Jon C. Muzio
1976	J	`jnl`	A ternary universal decision element. Notre Dame J. Formal Log. D. Michael Miller, Jon C. Muzio