D. M. H. Walker

74 papers A* 1A 18C 1Misc 18Journal 12Unranked 24

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. DFT Avijit Chakraborty, D. M. H. Walker
2017	Misc	`conf`	Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. VLSID Prasenjit Biswas, D. M. H. Walker
2015	—	`conf`	Impact of test compression on power supply noise control. DFTS Tengteng Zhang, D. M. H. Walker
2015	—	`conf`	Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. ACM Great Lakes Symposium on VLSI Avijit Chakraborty, D. M. H. Walker
2015	J	`jnl`	Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. J. Electron. Test. Tengteng Zhang, Yukun Gao, D. M. H. Walker
2015	J	`jnl`	Pseudo Functional Path Delay Test through Embedded Memories. J. Electron. Test. Yukun Gao, Tengteng Zhang, Punj Pokharel, Swati Chakraborty, D. M. H. Walker
2014	—	`conf`	Delay Test of Embedded Memories. NATW Yukun Gao, Tengteng Zhang, Swati Chakraborty, D. M. H. Walker
2014	—	`conf`	Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise. NATW Tengteng Zhang, Yukun Gao, D. M. H. Walker
2014	Misc	`conf`	Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. VLSID Kun Bian, D. M. H. Walker, Sunil P. Khatri
2013	—	`conf`	Mixed structural-functional path delay test generation and compaction. DFTS Kun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri
2012	C	`conf`	Maximizing crosstalk-induced slowdown during path delay test. ICCD Dibakar Gope, D. M. H. Walker
2011	Misc	`conf`	Levelized low cost delay test compaction considering IR-drop induced power supply noise. VTS Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker
2009	—	`conf`	Challenges in Delay Testing of Integrated Circuits. DFT D. M. H. Walker
2008	J	`jnl`	A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integr. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker
2008	Misc	`conf`	Dynamic Compaction for High Quality Delay Test. VTS Zheng Wang, D. M. H. Walker
2006	A	`conf`	Comparison of Delay Tests on Silicon. ITC Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore
2006	J	`jnl`	Estimation of fault-free leakage current using wafer-level spatial information. IEEE Trans. Very Large Scale Integr. Syst. Sagar S. Sabade, D. M. H. Walker
2006	A	`conf`	Power Supply Noise in Delay Testing. ITC Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger
2006	—	`conf`	Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits. MTV Hyun Sung Kim, D. M. H. Walker
2005	—	`conf`	A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. DFT Lei Wu, D. M. H. Walker
2005	A	`conf`	A vector-based approach for power supply noise analysis in test compaction. ITC Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2005	A	`conf`	I ITC Bin Xue, D. M. H. Walker
2005	—	`conf`	Is IDDQ Test of Microprocessors Feasible? MTV Bin Xue, D. M. H. Walker
2005	J	`jnl`	Longest-path selection for delay test under process variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2005	Misc	`conf`	Static Compaction of Delay Tests Considering Power Supply Noise. VTS Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker
2004	—	`conf`	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2004	Misc	`conf`	A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
2004	Misc	`conf`	Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. VLSI Design Sagar S. Sabade, D. M. H. Walker
2004	J	`jnl`	I J. Syst. Archit. Sagar S. Sabade, D. M. H. Walker
2004	J	`jnl`	I ACM Trans. Design Autom. Electr. Syst. Sagar S. Sabade, D. M. H. Walker
2004	A	`conf`	K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
2004	—	`conf`	Longest path selection for delay test under process variation. ASP-DAC Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2004	Misc	`conf`	On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. VTS Sagar S. Sabade, D. M. H. Walker
2004	—	`conf`	PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2003	Misc	`conf`	A Circuit Level Fault Model for Resistive Opens and Bridges. VTS Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2003	J	`jnl`	A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2003	A	`conf`	An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. ITC Wangqi Qiu, D. M. H. Walker
2003	—	`conf`	CROWNE: Current Ratio Outliers with Neighbor Estimator. DFT Sagar S. Sabade, D. M. H. Walker
2003	—	`conf`	Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. DFT Abhijit Prasad, D. M. H. Walker
2003	—	`conf`	CodSim -- A Combined Delay Fault Simulator. DFT Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
2003	Misc	`conf`	Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. VLSI Design Sagar S. Sabade, D. M. H. Walker
2003	—	`conf`	Testing the Path Delay Faults of ISCAS85 Circuit c6288. MTV Wangqi Qiu, D. M. H. Walker
2003	Misc	`conf`	Use of Multiple IDDQ Test Metrics for Outlier Identification. VTS Sagar S. Sabade, D. M. H. Walker
2002	Misc	`conf`	Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. VTS Sagar S. Sabade, D. M. H. Walker
2002	—	`conf`	Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. ASP-DAC/VLSI Design Sagar S. Sabade, D. M. H. Walker
2002	J	`jnl`	IDDQ Test: Will It Survive the DSM Challenge? IEEE Des. Test Comput. Sagar S. Sabade, D. M. H. Walker
2002	—	`conf`	Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. DFT Sagar S. Sabade, D. M. H. Walker
2001	A	`conf`	A practical built-in current sensor for I_DDQ testing. ITC Hoki Kim, D. M. H. Walker, David Colby
2001	—	`conf`	An efficient solution to the storage correspondence problem for large sequential circuits. ASP-DAC Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
2001	A	`conf`	FedEx - a fast bridging fault extractor. ITC Zoran Stanojevic, D. M. H. Walker
2001	A	`conf`	Improved wafer-level spatial analysis for I_DDQ limit setting. ITC Sagar S. Sabade, D. M. H. Walker
2000	A	`conf`	Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. ITC Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler
2000	Misc	`conf`	PROBE: A PPSFP Simulator for Resistive Bridging Faults. VTS Chul Young Lee, D. M. H. Walker
2000	Misc	`conf`	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. VTS Byungwoo Choi, D. M. H. Walker
1999	A	`conf`	Design for Yield and Reliability is MORE Important Than DFT. ITC D. M. H. Walker
1999	—	`conf`	IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. Asian Test Symposium Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
1999	A	`conf`	Resistive bridge fault modeling, simulation and test generation. ITC Vijay R. Sar-Dessai, D. M. H. Walker
1999	Misc	`conf`	Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. VTS Debashis Nayak, D. M. H. Walker
1998	—	`conf`	Accurate Fault Modeling and Fault Simulation of Resistive Bridges. DFT Vijay R. Sar-Dessai, D. M. H. Walker
1998	A	`conf`	Bridging Fault Detection in FPGA Interconnects Using FPGA Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
1998	A	`conf`	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. ITC Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
1998	J	`jnl`	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. IEEE Trans. Computers Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
1996	—	`conf`	Fatal Fault Probability Prediction for Array Based Designs. DFT Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker
1996	A	`conf`	Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. ITC Yuyun Liao, D. M. H. Walker
1996	Misc	`conf`	Improvement of SRAM-based failure analysis using calibrated Iddq testing. VTS Hari Balachandran, D. M. H. Walker
1996	Misc	`conf`	Optimal voltage testing for physically-based faults. VTS Yuyun Liao, D. M. H. Walker
1996	A	`conf`	Test Generation for Global Delay Faults. ITC G. M. Luong, D. M. H. Walker
1995	—	`conf`	Accurate yield estimation of circuits with redundancy. DFT Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly
1995	A	`conf`	IC Performance Prediction System. ITC V. Ramakrishnan, D. M. H. Walker
1995	A	`conf`	Yiel Learning via Functional Test Data. ITC Young-Jun Kwon, D. M. H. Walker
1993	Misc	`conf`	Estimation of reject ratio in testing of combinatorial circuits. VTS Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly
1993	J	`jnl`	The CDB/HCDB semiconductor wafer representation server. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas
1991	A*	`conf`	A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. DAC D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas
1986	J	`jnl`	VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. D. M. H. Walker, Stephen W. Director