D. Gracia Nirmala Rani

12 papers Misc 1Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Enhancing Digital Microfluidic Biochip Operations with Scheduling Interval Method.
VLSID
Nirmala N, D. Gracia Nirmala Rani
2022 J jnl
A C4.5 decision tree classifier based floorplanning algorithm for System-on-Chip design.
Microelectron. J.
J. Shanthi, D. Gracia Nirmala Rani, S. Rajaram
2022 J jnl
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning.
Integr.
J. Shanthi, D. Gracia Nirmala Rani, S. Rajaram
2022 J jnl
Design and analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications.
Trans. Emerg. Telecommun. Technol.
A. Andrew Roobert, P. Sherly Arunodhayamary, D. Gracia Nirmala Rani, M. Venkatesh, L. Jerart Julus
2021 J jnl
Design and analysis of a sleep and wake-up CMOS low noise amplifier for 5G applications.
Telecommun. Syst.
A. Andrew Roobert, D. Gracia Nirmala Rani
2021 J jnl
Design of 5-bit Flash ADC Using 180 nm Technology for Medical Applications.
Wirel. Pers. Commun.
G. Gifta, D. Gracia Nirmala Rani
2020 J jnl
Design and analysis of 0.9 and 2.3-GHz concurrent dual-band CMOS LNA for mobile communication.
Int. J. Circuit Theory Appl.
A. Andrew Roobert, D. Gracia Nirmala Rani
2019 J jnl
Design and optimisation of feedforward noise cancelling complementary metal oxide semiconductor LNA for 2.4 GHz WLAN applications.
IET Circuits Devices Syst.
A. Andrew Roobert, D. Gracia Nirmala Rani, S. Rajaram
2019 — ed.
VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers
VDAT
S. Rajaram, N. B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh
2018 — conf
Design of CMOS Based Biosensor for Implantable Medical Devices.
VDAT
G. Gifta, D. Gracia Nirmala Rani, Nifasath Farhana, R. Archana
2018 — conf
Design of CMOS based LNA for 5G Wireless Applications.
ICCBN
A. Andrew Roobert, D. Gracia Nirmala Rani, M. Divya, S. Rajaram
2013 J jnl
A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation.
Int. J. Comput. Appl. Technol.
D. Gracia Nirmala Rani, S. Rajaram