D. F. Wong - RankMe

164 papers A* 30A 53C 24Journal 25Unranked 30

Year	Rank	Type	Title / Venue / Authors
2004	—	`conf`	An ECO algorithm for eliminating crosstalk violations. ISPD Hua Xiang, Kai-Yuan Chao, D. F. Wong
2003	—	`conf`	A fast and accurate method for interconnect current calculation. ASP-DAC Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan
2003	J	`jnl`	Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
2003	A*	`conf`	Blade and razor: cell and interconnect delay analysis using current-based models. DAC John F. Croix, D. F. Wong
2003	—	`conf`	Floorplanning with power supply noise avoidance. ASP-DAC Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong
2003	A	`conf`	Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE Li-Da Huang, Hung-Ming Chen, D. F. Wong
2003	A	`conf`	Wire type assignment for FPGA routing. FPGA Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
2002	A	`conf`	A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
2002	A*	`conf`	An algorithm for integrated pin assignment and buffer planning. DAC Hua Xiang, D. F. Wong, Xiaoping Tang
2002	—	`conf`	Design hierarchy guided multilevel circuit partitioning. ISPD Yongseok Cheon, D. F. Wong
2002	A	`conf`	ECO algorithms for removing overlaps between power rails and signal wires. ICCAD Hua Xiang, Kai-Yuan Chao, D. F. Wong
2002	A*	`conf`	Floorplanning with alignment and performance constraints. DAC Xiaoping Tang, D. F. Wong
2002	A	`conf`	Incremental reconfiguration of multi-FPGA systems. FPGA K. K. Lee, D. F. Wong
2002	A	`conf`	Maze Routing with Buffer Insertion under Transition Time Constraints. DATE Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
2002	A	`conf`	On mask layout partitioning for electron projection lithography. ICCAD Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong
2002	A	`conf`	Shaping interconnect for uniform current density. ICCAD Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao
2002	—	`conf`	Timing-driven routing for FPGAs based on Lagrangian relaxation. ISPD Seokjin Lee, D. F. Wong
2001	A	`conf`	A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. ICCAD Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
2001	—	`conf`	A fast and accurate delay estimation method for buffered interconnects. ASP-DAC Youxin Gao, D. F. Wong
2001	A	`conf`	A graph based algorithm for optimal buffer insertion under accurate delay models. DATE Youxin Gao, D. F. Wong
2001	A	`conf`	An Algorithm for Simultaneous Pin Assignment and Routing. ICCAD Hua Xiang, Xiaoping Tang, D. F. Wong
2001	J	`jnl`	Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. Chris C. N. Chu, D. F. Wong
2001	—	`conf`	Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. ISPD Ruiqi Tian, Xiaoping Tang, D. F. Wong
2001	—	`conf`	FAST-SP: a fast algorithm for block placement based on sequence pair. ASP-DAC Xiaoping Tang, D. F. Wong
2001	—	`conf`	Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
2001	—	`conf`	Integrated power supply planning and floorplanning. ASP-DAC I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
2001	A	`conf`	LRoute: a delay minimal router for hierarchical CPLDs. FPGA K. K. Lee, D. F. Wong
2001	—	`conf`	Memory-efficient interconnect optimization. ASP-DAC Minghorng Lai, D. F. Wong
2001	J	`jnl`	Network flow based buffer planning. Integr. Xiaoping Tang, D. F. Wong
2001	A	`conf`	Slicing tree is a complete floorplan representation. DATE Minghorng Lai, D. F. Wong
2001	J	`jnl`	VLSI Circuit Performance Optimization by Geometric Programming. Ann. Oper. Res. Chris C. N. Chu, D. F. Wong
2000	J	`jnl`	A fast hypergraph min-cut algorithm for circuit partitioning. Integr. Wai-Kei Mak, D. F. Wong
2000	J	`jnl`	FPGA Partitioning with Complex Resource Constraints. VLSI Design Huiqun Liu, Kai Zhu, D. F. Wong
2000	A	`conf`	Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. DATE Xiaoping Tang, D. F. Wong, Ruiqi Tian
2000	A*	`conf`	Maze routing with buffer insertion and wiresizing. DAC Minghorng Lai, D. F. Wong
2000	A	`conf`	Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE I-Min Liu, Adnan Aziz, D. F. Wong
2000	A*	`conf`	Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. DAC Ruiqi Tian, D. F. Wong, Robert Boone
2000	A*	`conf`	Optimal low power X OR gate decomposition. DAC Hai Zhou, D. F. Wong
2000	—	`conf`	Planning buffer locations by network flows. ISPD Xiaoping Tang, D. F. Wong
2000	J	`jnl`	Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, Kai Zhu, D. F. Wong
2000	A	`conf`	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. DATE Youxin Gao, D. F. Wong
2000	—	`conf`	Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
1999	—	`conf`	A fast hypergraph minimum cut algorithm. ISCAS (6) Wai-Kei Mak, D. F. Wong
1999	A	`conf`	A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. ICCAD Huiqun Liu, D. F. Wong
1999	A	`conf`	Advances in transistor timing, simulation, and optimization (tutorial abstract). ICCAD Jacob White, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong
1999	C	`conf`	An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
1999	C	`conf`	An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. ICCD K. K. Lee, D. F. Wong
1999	A	`conf`	Circuit Partitioning for Dynamically Reconfigurable FPGAs. FPGA Huiqun Liu, D. F. Wong
1999	A*	`conf`	Error Bounded Padé Approximation via Bilinear Conformal Transformation. DAC Chung-Ping Chen, D. F. Wong
1999	J	`jnl`	Generation of Universal Series-Parallel Boolean Functions. J. ACM Fung Yu Young, Chris C. N. Chu, D. F. Wong
1999	A	`conf`	Integrated floorplanning and interconnect planning. ICCAD Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
1999	—	`conf`	Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ASP-DAC Youxin Gao, D. F. Wong
1999	—	`ed.`	Proceedings of the 1999 International Symposium on Physical Design, ISPD 1999, Monterey, CA, USA, April 12-14, 1999 ISPD D. F. Wong
1999	J	`jnl`	Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. Integr. Youxin Gao, D. F. Wong
1999	A*	`conf`	Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
1999	—	`conf`	Slicing Floorplans with Boundary Constraint. ASP-DAC Fung Yu Young, D. F. Wong
1999	—	`conf`	Slicing floorplans with range constraint. ISPD Fung Yu Young, D. F. Wong
1998	A	`conf`	A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE Chris C. N. Chu, D. F. Wong
1998	A	`conf`	Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA Huiqun Liu, Kai Zhu, D. F. Wong
1998	A*	`conf`	Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. DAC Madhukar R. Korupolu, K. K. Lee, D. F. Wong
1998	A	`conf`	Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
1998	A*	`conf`	Global Routing with Crosstalk Constraints. DAC Hai Zhou, D. F. Wong
1998	A	`conf`	Graph matching-based algorithms for FPGA segmentation design. ICCAD Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
1998	—	`conf`	Greedy wire-sizing is linear time. ISPD Chris C. N. Chu, D. F. Wong
1998	C	`conf`	Integrated partitioning and scheduling for hardware/software co-design. ICCD Huiqun Liu, D. F. Wong
1998	J	`jnl`	Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. VLSI Design Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
1998	A	`conf`	Network flow based circuit partitioning for time-multiplexed FPGAs. ICCAD Huiqun Liu, D. F. Wong
1998	J	`jnl`	Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. Hai Zhou, D. F. Wong
1998	A	`conf`	Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA Wai-Kei Mak, D. F. Wong
1998	C	`conf`	Performance-driven board-level routing for FPGA-based logic emulation. ICCD Wai-Kei Mak, D. F. Wong
1998	A	`conf`	Shaping a VLSI wire to minimize delay using transmission line model. ICCAD Youxin Gao, D. F. Wong
1998	A	`conf`	Slicing floorplans with pre-placed modules. ICCAD Fung Yu Young, D. F. Wong
1998	C	`conf`	Timing-driven routing for symmetrical-array-based FPGAs. ICCD Kai Zhu, Yao-Wen Chang, D. F. Wong
1997	A*	`conf`	A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. DAC John F. Croix, D. F. Wong
1997	J	`jnl`	A graph theoretic approach to feed-through pin assignment. Integr. Yao-Ping Chen, D. F. Wong
1997	—	`conf`	A matrix synthesis approach to thermal placement. ISPD Chris C. N. Chu, D. F. Wong
1997	A	`conf`	A new approach to simultaneous buffer insertion and wire sizing. ICCAD Chris C. N. Chu, D. F. Wong
1997	A	`conf`	An exact gate decomposition algorithm for low-power technology mapping. ICCAD Hai Zhou, D. F. Wong
1997	J	`jnl`	Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. Wai-Kei Mak, D. F. Wong
1997	C	`conf`	Channel Segmentation Design for Symmentrical FPGAs. ICCD Wai-Kei Mak, D. F. Wong
1997	—	`conf`	Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD Chris C. N. Chu, D. F. Wong
1997	C	`conf`	Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi
1997	C	`conf`	Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD Hai Zhou, D. F. Wong
1997	J	`jnl`	How good are slicing floorplans? Integr. F. Y. Young, D. F. Wong
1997	—	`conf`	How good are slicing floorplans?. ISPD Fung Yu Young, D. F. Wong
1997	—	`conf`	Network flow based multi-way partitioning with area and pin constraints. ISPD Huiqun Liu, D. F. Wong
1997	J	`jnl`	On retiming for FPGA logic module minimization. Integr. Yao-Ping Chen, D. F. Wong
1997	C	`conf`	On the Construction of Universal Series-Parallel Functions for Logic Module Design. ICCD Fung Yu Young, D. F. Wong
1997	A*	`conf`	Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC Chung-Ping Chen, D. F. Wong
1997	A	`conf`	Optimal shape function for a bi-directional wire under Elmore delay model. ICCAD Youxin Gao, D. F. Wong
1996	—	`conf`	An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion. ED&TC Y. P. Chen, D. F. Wong
1996	A	`conf`	An optimal algorithm for river routing with crosstalk constraints. ICCAD Hai Zhou, D. F. Wong
1996	A*	`conf`	Delay Minimal Decomposition of Multiplexers in Technology Mapping. DAC Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy
1996	A*	`conf`	Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC Chung-Ping Chen, Yao-Wen Chang, D. F. Wong
1996	A	`conf`	Minimum replication min-cut partitioning. ICCAD Wai-Kei Mak, D. F. Wong
1996	C	`conf`	Multiplexor Network Generation in High Level Synthesis. ICCD Yung-Ming Fang, D. F. Wong
1996	A*	`conf`	Optimal Wire-Sizing Formular Under the Elmore Delay Model. DAC Chung-Ping Chen, Yao-Ping Chen, D. F. Wong
1996	A	`conf`	Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD Chung-Ping Chen, Hai Zhou, D. F. Wong
1996	J	`jnl`	Series-parallel functions and FPGA logic module design. ACM Trans. Design Autom. Electr. Syst. Shashidhar Thakur, D. F. Wong
1996	J	`jnl`	Simultaneous area and delay minimum K-LUT mapping for K-exact networks. Integr. Shashidhar Thakur, D. F. Wong
1996	A	`conf`	Universal Logic Modules for Series-Parallel Functions. FPGA Shashidhar Thakur, D. F. Wong
1996	A	`conf`	Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA Yao-Wen Chang, D. F. Wong, C. K. Wong
1996	J	`jnl`	Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, D. F. Wong, C. K. Wong
1995	C	`conf`	A Graph Theoretic Approach to Feed-Through Pin Assignment. ISCAS Yao-Ping Chen, D. F. Wong
1995	C	`conf`	An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. ISCAS Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
1995	A	`conf`	Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD Wai-Kei Mak, D. F. Wong
1995	—	`conf`	Circuit clustering for delay minimization under area and pin constraints. ED&TC Honghua Yang, D. F. Wong
1995	C	`conf`	Design and analysis of FPGA/FPIC switch modules. ICCD Yao-Wen Chang, D. F. Wong, C. K. Wong
1995	C	`conf`	FPGA global routing based on a new congestion metric. ICCD Yao-Wen Chang, D. F. Wong, C. K. Wong
1995	C	`conf`	Floorplanning for Low Power Designs. ISCAS Kai-Yuan Chao, D. F. Wong
1995	A	`conf`	New algorithms for min-cut replication in partitioned circuits. ICCAD Hannah Honghua Yang, D. F. Wong
1995	A	`conf`	On Designing ULM-based FPGA Logic Modules. FPGA Shashidhar Thakur, D. F. Wong
1995	A*	`conf`	On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC Wai-Kei Mak, D. F. Wong
1995	A	`conf`	Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD Kai-Yuan Chao, D. F. Wong
1995	C	`conf`	Simultaneous area and delay minimum K-LUT mapping for K-exact networks. ICCD Shashidhar Thakur, D. F. Wong
1995	C	`conf`	Thermal placement for high-performance multichip modules. ICCD Kai-Yuan Chao, D. F. Wong
1994	A	`conf`	A new global routing algorithm for FPGAs. ICCAD Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
1994	—	`conf`	Algorithms for a switch module routing problem. EURO-DAC Shashidhar Thakur, D. F. Wong, S. Muthukrishnan
1994	J	`jnl`	Channel Density Minimization by Pin Permutation. VLSI Design Yang Cai, D. F. Wong, Jason Cong
1994	A*	`conf`	Clock Skew Minimization During FPGA Placement. DAC Kai Zhu, D. F. Wong
1994	A	`conf`	Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD Hannah Honghua Yang, D. F. Wong
1994	A	`conf`	Efficient network flow based min-cut balanced partitioning. ICCAD Honghua Yang, D. F. Wong
1994	A	`conf`	Layer assignment for high-performance multi-chip modules. ICCAD Kai-Yuan Chao, D. F. Wong
1994	C	`conf`	On Retiming for FPGA Logic Module Minimization. ICCD Yao-Ping Chen, D. F. Wong
1994	C	`conf`	Over-the-Cell Routing with Cell Orientations Consideration. ISCAS T. W. Her, D. F. Wong
1994	A	`conf`	Simultaneous functional-unit binding and floorplanning. ICCAD Yung-Ming Fang, D. F. Wong
1994	A*	`conf`	Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. DAC Kai Zhu, D. F. Wong
1993	C	`conf`	A Graph Partitioning Problem for Multiple-chip Design. ISCAS Yao-Ping Chen, Ting-Chi Wang, D. F. Wong
1993	—	`ch.`	A note on the Complexity of Stockmeyer's floorplan Optimization Technique. Algorithmic Aspects of VLSI Layout Ting-Chi Wang, D. F. Wong
1993	—	`conf`	Cell area minimization by transistor folding. EURO-DAC T. W. Her, D. F. Wong
1993	—	`conf`	Fast Boolean matching for field-programmable gate arrays. EURO-DAC Kai Zhu, D. F. Wong
1993	J	`jnl`	Graph-based techniques to speed up floorplan area optimization. Integr. Ting-Chi Wang, D. F. Wong
1993	A*	`conf`	HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. DAC Glenn G. Lai, Donald S. Fussell, D. F. Wong
1993	C	`conf`	On optimal approximation of orthogonal polygons. ISCAS Yao-Ping Chen, D. F. Wong
1993	—	`conf`	On over-the-cell channel routing. EURO-DAC Ting-Chi Wang, D. F. Wong, Yachyang Sun, C. K. Wong
1993	A*	`conf`	Optimal Clustering for Delay Minimization. DAC Rajmohan Rajaraman, D. F. Wong
1993	A	`conf`	Switch module design with application to two-dimensional segmentation design. ICCAD Kai Zhu, D. F. Wong, Yao-Wen Chang
1992	A*	`conf`	A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC Ting-Chi Wang, D. F. Wong
1992	C	`conf`	Channel Density Minimization by Pin Permutation. ICCD Yang Cai, D. F. Wong
1992	A	`conf`	On channel segmentation design for row-based FPGAs. ICCAD Kai Zhu, D. F. Wong
1991	A*	`conf`	A General Multi-Layer Area Router. DAC Mohankumar Guruswamy, D. F. Wong
1991	C	`conf`	Area Optimization for Higher Order Hierarchical Floorplans. ICCD Khe-Sing The, D. F. Wong
1991	—	`conf`	Efficient shape curve construction in floorplan design. EURO-DAC Ting-Chi Wang, D. F. Wong
1991	A	`conf`	Minimizing Channel Density by Shifting Blocks and Terminals. ICCAD Yang Cai, D. F. Wong
1991	A*	`conf`	On Minimizing the Number of L-Shaped Channels. DAC Yang Cai, D. F. Wong
1991	C	`conf`	On the Manisfestation of Faults to Errors in Signature Analysis. ICCD John C. Chan, Baxter F. Womack, D. F. Wong
1991	A	`conf`	Optimal Module Implementation and Its Application to Transistor Placement. ICCAD T. W. Her, D. F. Wong
1991	J	`jnl`	Probabilistic Analysis of a Grouping Algorithm. Algorithmica D. F. Wong, Edward M. Reingold
1990	A*	`conf`	A Channel/Switchbox Definition Algorithm for Building-Block Layout. DAC Yang Cai, D. F. Wong
1990	A*	`conf`	An Optimal Algorithm for Floorplan Area Optimization. DAC Ting-Chi Wang, D. F. Wong
1990	A	`conf`	An Optimal Channel Pin Assignment Algorithm. ICCAD Yang Cai, D. F. Wong
1990	J	`jnl`	Generating more compactable channel routing solutions. Integr. Jingsheng Cong, D. F. Wong
1990	A	`conf`	Optimal Orientations of Transistor Chains. ICCAD T. W. Her, D. F. Wong, T. H. Freeman
1990	—	`conf`	Optimal via-shifting in channel compaction. EURO-DAC Yang Cai, D. F. Wong
1990	A	`conf`	Topological Routing Using Geometric Information. ICCAD Shinichiro Haruyama, D. F. Wong, Donald S. Fussell
1989	A	`conf`	An algorithm for hierarchical floorplan design. ICCAD D. F. Wong, Khe-Sing The
1989	J	`jnl`	An enhanced bottom-up algorithm for floorplan design. Integr. Thomas R. Mueller, D. F. Wong, C. L. Liu
1989	A*	`conf`	Efficient Floorplan Area Optimization. DAC D. F. Wong, P. S. Sakhamuri
1989	J	`jnl`	Floorplan Design of VLSI Circuits. Algorithmica D. F. Wong, C. L. Liu
1989	A*	`conf`	VIA Minimization by Layout Modification. DAC Khe-Sing The, D. F. Wong, Jason Cong
1988	A*	`conf`	How to Obtain More Compactable Channel Routing Solutions. DAC Jingsheng Cong, D. F. Wong
1987	A*	`conf`	Array Optimization for VLSI Synthesis. DAC D. F. Wong, C. L. Liu
1986	A*	`conf`	A new algorithm for floorplan design. DAC D. F. Wong, C. L. Liu
1986	J	`jnl`	Compacted channel routing with via placement restrictions. Integr. D. F. Wong, C. L. Liu