Cédric Bourrasset

16 papers Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2018 J jnl
Bio-inspired heterogeneous architecture for real-time pedestrian detection applications.
J. Real Time Image Process.
Luca Maggiani, Cédric Bourrasset, Jean-Charles Quinton, François Berry, Jocelyn Sérot
2018 — conf
Requirements for an Enterprise AI Benchmark.
TPCTC
Cédric Bourrasset, France Boillod-Cerneux, Ludovic Sauge, Myrtille Deldossi, Francois Wellenreiter, Rajesh Bordawekar, Susan Malaika, Jean-Armand Broyelle, Marc West, Brian M. Belgodere
2017 J jnl
A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA.
CoRR
Kamel Abdelouahab, Cédric Bourrasset, Maxime Pelcat, François Berry, Jean-Charles Quinton, Jocelyn Sérot
2017 J jnl
Hardware Automated Dataflow Deployment of CNNs.
CoRR
Kamel Abdelouahab, Maxime Pelcat, Jocelyn Sérot, François Berry, Cédric Bourrasset, Jean-Charles Quinton
2017 J jnl
Tactics to Directly Map CNN Graphs on Embedded FPGAs.
IEEE Embed. Syst. Lett.
Kamel Abdelouahab, Maxime Pelcat, Jocelyn Sérot, Cédric Bourrasset, François Berry
2017 J jnl
Tactics to Directly Map CNN graphs on Embedded FPGAs.
CoRR
Kamel Abdelouahab, Maxime Pelcat, Cédric Bourrasset, François Berry, Jocelyn Sérot
2016 — conf
A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA.
ICDSC
Kamel Abdelouahab, Cédric Bourrasset, Maxime Pelcat, François Berry, Jean-Charles Quinton, Jocelyn Sérot
2016 J jnl
Dataflow object detection system for FPGA-based smart camera.
IET Circuits Devices Syst.
Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry
2016 — conf
Design productivity of a high level synthesis compiler versus HDL.
SAMOS
Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry
2016 J jnl
High-level dataflow programming for real-time image processing on smart cameras.
J. Real Time Image Process.
Jocelyn Sérot, François Berry, Cédric Bourrasset
2016 — —
Le modèle flot de données appliqué à la synthèse haut-niveau pour le traitement d'images sur caméra intelligente à base de FPGA. Application aux systèmes d'apprentissage supervisés. (High level synthesis of dataflow programs for image processing on FPGA-based smart camera. Application to machine learning).
Cédric Bourrasset
2015 J jnl
HOG-Dot: A Parallel Kernel-Based Gradient Extraction for Embedded Image Processing.
IEEE Signal Process. Lett.
Luca Maggiani, Cédric Bourrasset, Matteo Petracca, François Berry, Paolo Pagano, Claudio Salvadori
2015 — conf
Parallel image gradient extraction core for FPGA-based smart cameras.
ICDSC
Luca Maggiani, Cédric Bourrasset, François Berry, Jocelyn Sérot, Matteo Petracca, Claudio Salvadori
2013 — conf
Distributed FPGA-based smart camera architecture for computer vision applications.
ICDSC
Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry, Paolo Pagano
2013 — conf
DreamCAM: A FPGA-based platform for smart camera networks.
ICDSC
Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry, Paolo Pagano
2013 — conf
FPGA-based smart camera mote for pervasive wireless network.
ICDSC
Cédric Bourrasset, Jocelyn Sérot, François Berry