Cyrus Bamji

21 papers A* 7A 2C 1Misc 4Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2004 — conf
A Time-Of-Flight Depth Sensor - System Description, Issues and Solutions.
CVPR Workshops
S. Burak Gokturk, Hakan Yalcin, Cyrus Bamji
2001 A* conf
An Advanced Timing Characterization Method Using Mode Dependency.
DAC
Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
2001 J jnl
Fast and accurate timing characterization using functionalinformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
2001 J jnl
Technology mapping for high-performance static CMOS and pass transistor logic designs.
IEEE Trans. Very Large Scale Integr. Syst.
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
2000 A conf
Transistor-Level Timing Analysis Using Embedded Simulation.
ICCAD
Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin
1999 A* conf
Functional Timing Analysis for IP Characterization.
DAC
Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah
1998 C conf
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic.
ICCD
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
1998 Misc conf
An Improved Cost Heuristic for Transistor Sizing.
VLSI Design
Cyrus Bamji, Manjit Borah
1998 — conf
Combined transistor sizing with buffer insertion for timing optimization.
CICC
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
1998 Misc conf
Incremental Autojogging using Range Spaces.
VLSI Design
Cyrus Bamji, Ravi Varadarajan
1998 J jnl
Interleaving buffer insertion and transistor sizing into a single optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
1997 — conf
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs.
ISPD
Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar
1996 A* conf
Enhanced Network Flow Algorithm for Yield Optimization.
DAC
Cyrus Bamji, Enrico Malavasi
1994 Misc conf
GLOVE: A Graph-Based Layout Verifier.
VLSI Design
Cyrus Bamji, Jonathan Allen
1993 A* conf
MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction.
DAC
Cyrus Bamji, Ravi Varadarajan
1992 A conf
Cloning techniques for hierarchical compaction.
ICCAD
Ravi Varadarajan, Cyrus Bamji
1992 A* conf
Hierarchical Pitchmatching Compaction Using Minimum Design.
DAC
Cyrus Bamji, Ravi Varadarajan
1989 A* conf
GRASP: A Grammar-based Schematic Parser.
DAC
Cyrus Bamji, Jonathan Allen
1989 — —
Graph-based representations and coupled verification of VLSI schematics and layouts.
Cyrus Bamji
1985 A* conf
A design by example regular structure generator.
DAC
Cyrus Bamji, Charles E. Hauck, Jonathan Allen
1985 Misc conf
The systematic exploration of pipelined array multiplier performance.
ICASSP
Charles E. Hauck, Cyrus Bamji, Jonathan Allen