Cyrille Chavet

45 papers A 3B 1C 7Misc 6Journal 14Unranked 13
YearRankTypeTitle / Venue / Authors
2025 J jnl
Exploring the Contribution of Hardware Shuffling in Securing Low-Cost Symmetric Encryption Devices against Power-Based Side-Channel Attacks: Case Study of an AES-128 on FPGA.
ACM Trans. Reconfigurable Technol. Syst.
Vianney Lapôtre, Cyrille Chavet, Ghita Harcha, Philippe Coussy
2025 J jnl
Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors.
IEEE Access
Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Philippe Coussy
2024 C conf
WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU).
FIE
Klaus Hofmann, Ferdinand Keil, David Riehl, Alicja Michalowska-Forsyth, Nikolaus Czepl, Sarah Woywod, Dominik Zupan, Mario R. Casu, Carlo Ricciardi, Massimo Violante, Mariagrazia Graziano, Yuri Ardesi, Fabrizio Mo, Dominik Berger, Sabine Sill, Volker Visotschnig, Panagiota Morfouli, Liliana Prejbeanu, Katell Morin-Allory, Cyrille Chavet, Davide Bucci, Skandar Basrour, Jean-Christophe Crebier, Nhu-Huan Nguyen, Ernesto Quisbert-Trujillo, Christian Defélix, Isabelle Corbett-Etchevers, Johannes Sturm, Jens Peter Konrath, Ulla Birnbacher, Thomas Klinger, Wolfgang Werth, Jorge Fernandes, Marcelino B. Santos, Antonio Rubio, Alba Pagès-Zamora, Josep Pegueroles, Jordi Salazar, Beatriz Otero, J. Manuel Moreno, X. Aragones, Israel Martin, Aleix Sole, Dunja Suttnig, Julia Calabro, Floriberto Lima, Eric Jouseau, François Cerisier, Cristian Rivier, Sepp Eisenriegler, Harald Reichl, Miroslav Macan, Dubravko Kruselj, Mladen Puskaric, Mirjana Tatalovic, Vinko Zelenicic, Bernd Deutschmann
2021 J jnl
Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards.
J. Signal Process. Syst.
Hassan Harb, Cyrille Chavet
2021 — conf
Extended RISC-V hardware architecture for future digital communication systems.
5GWF
Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy
2020 Misc conf
Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards.
ICASSP
Hassan Harb, Cyrille Chavet
2020 J jnl
Fully Parallel Circular-Shift Rotation Network for Communication Standards.
IEEE Trans. Circuits Syst.
Hassan Harb, Cyrille Chavet
2020 C conf
Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation.
ISCAS
Ghita Harcha, Vianney Lapôtre, Cyrille Chavet, Philippe Coussy
2019 J jnl
Clone-Based Encoded Neural Networks to Design Efficient Associative Memories.
IEEE Trans. Neural Networks Learn. Syst.
Hugues Wouafo, Cyrille Chavet, Philippe Coussy
2019 Misc conf
Solving Memory Access Conflicts in LTE-4G Standard.
ICASSP
Cyrille Chavet, Fabrice Lozachmeur, T. Barguil, A. S. Hussein, Philippe Coussy
2017 — conf
Efficient scalable hardware architecture for highly performant encoded neural networks.
SiPS
Hugues Wouafo, Cyrille Chavet, Philippe Coussy, Robin Danilo
2016 A conf
A dynamically reconfigurable ECC decoder architecture.
DATE
Awais Sani, Philippe Coussy, Cyrille Chavet
2016 — conf
Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection.
DASIP
Robin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia, Philippe Coussy
2015 J jnl
Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories.
ACM J. Emerg. Technol. Comput. Syst.
Philippe Coussy, Cyrille Chavet, Hugues Nono Wouafo, Laura Conde-Canencia
2015 C conf
Improving storage of patterns in recurrent neural networks: Clone-based model and architecture.
ISCAS
Hugues Wouafo, Cyrille Chavet, Philippe Coussy
2015 A conf
In-place memory mapping approach for optimized parallel hardware interleaver architectures.
DATE
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani
2014 — conf
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures.
ACM Great Lakes Symposium on VLSI
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy
2014 — conf
A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code.
ICECS
Mickael Lanoe, Matteo Bordin, Dominique Heller, Philippe Coussy, Cyrille Chavet
2014 Misc conf
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.
ICASSP
Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy
2013 J jnl
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm.
IEEE Trans. Signal Process.
Awais Hussain Sani, Philippe Coussy, Cyrille Chavet
2013 — conf
A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller.
SiPS
Aroua Briki, Cyrille Chavet, Philippe Coussy
2013 — conf
A memory mapping approach for network and controller optimization in parallel interleaver architectures.
ACM Great Lakes Symposium on VLSI
Aroua Briki, Cyrille Chavet, Philippe Coussy
2013 B conf
Dynamic branch prediction for high-level synthesis.
FPL
Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo
2013 J jnl
Introduction de la prédiction de branchement dans la synthèse de haut niveau.
Tech. Sci. Informatiques
Vianney Lapotre, Philippe Coussy, Cyrille Chavet
2013 Misc conf
On-chip implementation of memory mapping algorithm to support flexible decoder architecture.
ICASSP
Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet
2012 — conf
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.
SiPS
Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo
2012 — conf
A design approach dedicated to network-based and conflict-free parallel interleavers.
ACM Great Lakes Symposium on VLSI
Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin
2012 C conf
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters.
DSD
Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini
2011 Misc conf
A methodology based on Transportation problem modeling for designing parallel interleaver architectures.
ICASSP
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2011 C conf
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture.
ISCAS
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2011 — conf
High-Level Synthesis: On the path to ESL design.
ASICON
Philippe Coussy, Dominique Heller, Cyrille Chavet
2010 C conf
A memory mapping approach for parallel interleaver design with multiples read and write accesses.
ISCAS
Cyrille Chavet, Philippe Coussy
2010 — conf
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach.
ICECS
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2010 J jnl
High-Level Synthesis for Designing Multimode Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet
2010 J jnl
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures
CoRR
Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard
2010 Misc conf
Static Address Generation Easing: a design methodology for parallel interleaver architectures.
ICASSP
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 J jnl
A Design Methodology for Space-Time Adapter
CoRR
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 J jnl
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver
CoRR
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 C conf
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver.
ISCAS
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 A conf
A design flow dedicated to multi-mode architectures for DSP applications.
ICCAD
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
2007 — conf
A design methodology for space-time adapter.
ACM Great Lakes Symposium on VLSI
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 J jnl
Application of a design space exploration tool to enhance interleaver generation
CoRR
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 — conf
Application of a design space exploration tool to enhance interleaver generation.
EUSIPCO
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 J jnl
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels
CoRR
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 — —
Synthèse automatique d'interfaces de communication matérielles pour la conception d'applications du domaine du traitement du signal. (Automatic synthesis of hardware communication interfaces for Data Signal Processing applications).
Cyrille Chavet