| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2013 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2013 | — | conf |
ISSoC
|
| 2012 | J | jnl |
Integr.
|
| 2011 | J | jnl |
J. Parallel Distributed Comput.
|
| 2011 | — | conf |
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs.
SBCCI
|
| 2011 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2011 | J | jnl |
J. Low Power Electron.
|
| 2011 | C | conf |
ISCAS
|
| 2010 | B | conf |
FPL
|
| 2010 | A | conf |
DATE
|
| 2010 | — | conf |
PATMOS
|
| 2010 | — | conf |
ICECS
|
| 2010 | C | conf |
ISCAS
|
| 2009 | — | conf |
ICECS
|
| 2009 | J | jnl |
Microelectron. J.
|
| 2007 | J | jnl |
J. Electron. Test.
|
| 2007 | — | conf |
MSE
|
| 2007 | C | conf |
VLSI-SoC
|
| 2007 | C | conf |
VLSI-SoC
|
| 2006 | — | conf |
ICECS
|
| 2006 | — | conf |
LATW
|
| 2006 | C | conf |
IOLTS
|
| 2005 | C | conf |
VLSI-SoC
|
| 2005 | C | conf |
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.
IOLTS
|
| 2004 | — | conf |
PATMOS
|
| 2004 | — | conf |
Automatic Full-Custom Layout Generation of Static CMOS Circuits Targeting Delay and Power Reduction.
IFIP Student Forum
|
| 2003 | C | conf |
VLSI-SOC
|
| 2003 | — | conf |
VLSI-SoC (Selected Papers)
|
| 2003 | — | conf |
SBCCI
|