Costas Efstathiou

67 papers B 1C 6Journal 20Unranked 40

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	On the Static CMOS Implementation of Magnitude Comparators. PATMOS Costas Efstathiou, Yiorgos Tsiatouhas
2018	—	`conf`	Low Power and High Speed Static CMOS Digital Magnitude Comparators. ICECS Costas Efstathiou, K. Dimolikas, Christoforos Papaioannou, Yiorgos Tsiatouhas
2018	—	`conf`	SIC pair generation in near-optimal time with carry-look ahead adders. DTIS Ioannis Voyiatzis, Costas Efstathiou
2017	—	`conf`	On the generation of binary functions with low-overhead. DTIS Ioannis Voyiatzis, Costas Efstathiou
2016	—	`conf`	Low Cost Boolean Function generation. PCI Ioannis Voyiatzis, Costas Efstathiou
2016	—	`conf`	Software-based SIC pair Generation. PCI Ioannis Voyiatzis, Costas Efstathiou, Kiriakos Patriarcheas
2015	—	`conf`	A concurrent BIST scheme for read only memories. DTIS Ioannis Voyiatzis, Cleo Sgouropoulou, Costas Efstathiou
2015	—	`conf`	Accumulator-based generation for serial TPG. Panhellenic Conference on Informatics Ioannis Voyiatzis, Costas Efstathiou
2015	—	`conf`	On the use of hard faults to generate test sets. Panhellenic Conference on Informatics Ioannis Voyiatzis, Costas Efstathiou
2015	—	`conf`	Test set embedding into hardware generated sequences using an embedding algorithm. DTIS Ioannis Voyiatzis, Dimitris J. Kavvadias, S. Sinitos, K. Vlahantonis, P. Kyrkos, Cleo Sgouropoulou, Costas Efstathiou
2014	—	`conf`	Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs. DTIS Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
2014	—	`conf`	High performance MAC designs. IDT Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kiamal Z. Pekmestzi, Costas Efstathiou
2014	J	`jnl`	Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells. IEEE Trans. Very Large Scale Integr. Syst. Ioannis Voyiatzis, Costas Efstathiou
2014	—	`conf`	Low overhead output response compaction in RAS architectures. DTIS Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
2014	—	`conf`	Stealth Assessment of Hardware Trojans in simple Processors. Panhellenic Conference on Informatics I. Nikopoulos, Athanasios Milidonis, Costas Efstathiou, Cleo Sgouropoulou, Ioannis Voyiatzis
2013	C	`conf`	A low-cost input vector monitoring concurrent BIST scheme. IOLTS Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
2013	J	`jnl`	An effective two-pattern test generator for Arithmetic BIST. Comput. Electr. Eng. Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis
2013	—	`conf`	Embedding test vectors in accumulator - based TPG using progressive search. DTIS Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
2013	J	`jnl`	New High-Speed Multioutput Carry Look-Ahead Adders. IEEE Trans. Circuits Syst. II Express Briefs Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas
2013	J	`jnl`	On the design of modulo 2 Comput. Electr. Eng. Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi
2013	—	`conf`	Symmetric transparent online BIST for arrays of word-organized RAMs. DTIS Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
2013	—	`conf`	Test set embedding into accumulator-generated sequences targeting hard-to-detect faults. IDT Ioannis Voyiatzis, Stelios Neophytou, Maria K. Michael, Stavros Hadjitheophanous, Cleo Sgouropoulou, Costas Efstathiou
2013	—	`conf`	Transparent testing for intra-word memory faults. IDT Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
2012	—	`conf`	A novel architecture to reduce test time in march-based SRAM tests. DTIS Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas, Cleo Sgouropoulou
2012	—	`conf`	ALU based address generation for RAMs. DTIS Ioannis Voyiatzis, Costas Efstathiou, Said Hamdioui, Cleo Sgouropoulou
2012	J	`jnl`	Arithmetic module-based built-in self test architecture for two-pattern testing. IET Comput. Digit. Tech. Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis
2012	—	`conf`	Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching. Panhellenic Conference on Informatics Ioannis Voyiatzis, Kyriakos Axiotis, Nikolaos S. Papaspyrou, Hera Antonopoulou, Costas Efstathiou
2012	—	`conf`	Test set embedding into low-power sequences based on a traveling salesman problem formulation. DTIS Ioannis Voyiatzis, Costas Efstathiou, Dimitris Magos, Cleo Sgouropoulou
2012	—	`conf`	Test vector embedding in accumulators with stored carry in O(1) time. DTIS Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
2011	B	`conf`	A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture. ETS Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou
2010	J	`jnl`	An efficient architecture for accumulator-based test generation of SIC pairs. Microelectron. J. Ioannis Voyiatzis, Costas Efstathiou
2010	—	`conf`	Efficient modulo 2 ICECS Costas Efstathiou
2010	J	`jnl`	Fast modulo 2 Integr. Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
2010	—	`conf`	On Embedding Test Sets into Hardware Generated Sequences. Panhellenic Conference on Informatics Dimitris J. Kavvadias, S. Sinitos, Ioannis Voyiatzis, Hera Antonopoulou, Costas Efstathiou
2009	J	`jnl`	Efficient modulo 2 Integr. Haridimos T. Vergos, Costas Efstathiou
2008	J	`jnl`	A Unifying Approach for Weighted and Diminished-1 Modulo 2 IEEE Trans. Circuits Syst. II Express Briefs Haridimos T. Vergos, Costas Efstathiou
2008	—	`conf`	Efficient modulo 2 ICECS Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
2007	J	`jnl`	Design of efficient modulo 2 IET Comput. Digit. Tech. Haridimos T. Vergos, Costas Efstathiou
2007	C	`conf`	Implementation of HSSec: a high-speed cryptographic co-processor. ETFA Athanasios P. Kakarountas, Haralambos Michail, Costas E. Goutis, Costas Efstathiou
2007	—	`conf`	SecurID Authenticator: On the Hardware Implementation Efficiency. ICECS Nicolas Sklavos, Costas Efstathiou
2007	J	`jnl`	Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
2006	C	`conf`	Novel Modulo 2 DSD Haridimos T. Vergos, Costas Efstathiou
2005	J	`jnl`	Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2005	—	`conf`	New architectures for modulo 2N - 1 adders. ICECS Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2005	J	`jnl`	On the Design of Efficient Modular Adders. J. Circuits Syst. Comput. Haridimos T. Vergos, Costas Efstathiou
2004	C	`conf`	Diminished-1 Modulo 2 DSD Haridimos T. Vergos, Costas Efstathiou
2004	J	`jnl`	Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2004	J	`jnl`	Modified Booth Modulo 2 IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2003	—	`conf`	A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003	—	`conf`	A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks. MMNS K. Katzourakis, George Kormentzas, Kimon P. Kontovasilis, Costas Efstathiou
2003	—	`conf`	A systematic methodology for designing area-time efficient parallel-prefix modulo 2 ISCAS (5) Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003	C	`conf`	An Efficient BIST scheme for High-Speed Adders. IOLTS Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
2003	J	`jnl`	Deterministic BIST for RNS Adders. IEEE Trans. Computers Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
2003	—	`conf`	Efficient BIST schemes for RNS datapaths. ISCAS (5) Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
2003	—	`conf`	Efficient modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2003	J	`jnl`	Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2002	J	`jnl`	Diminished-One Modulo 2 IEEE Trans. Computers Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
2002	—	`conf`	Ling adders in CMOS standard cell technologies. ICECS Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2001	—	`conf`	A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
2001	—	`conf`	Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
2001	C	`conf`	High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2001	—	`conf`	On the design of modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2000	J	`jnl`	High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
2000	—	`conf`	Modified Booth 1's complement and modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos
2000	—	`conf`	On Testability of Multiple Precharged Domino Logic. ISQED Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
1990	J	`jnl`	An Efficient TSC 1-out-of-3 Code Checker. IEEE Trans. Computers Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis
1984	—	`conf`	Modular design of totally self-checking checkers for 1-out-of-n codes. Fehlertolerierende Rechensysteme Costas Efstathiou, Constantine Halatsis