Cong Xu

44 papers A* 12A 10C 2Journal 11Unranked 9
YearRankTypeTitle / Venue / Authors
2022 J jnl
Memory Scaling of Cloud-Based Big Data Systems: A Hybrid Approach.
IEEE Trans. Big Data
Xinying Wang, Cong Xu, Ke Wang, Feng Yan, Dongfang Zhao
2019 J jnl
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst.
Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie, Shaojun Wei
2018 J jnl
SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning.
CoRR
Wei Wen, Yandan Wang, Feng Yan, Cong Xu, Yiran Chen, Hai Li
2018 — conf
Toward Cost-Effective Memory Scaling in Clouds: Symbiosis of Virtual and Physical Memory.
IEEE CLOUD
Xinying Wang, Cong Xu, Ke Wang, Feng Yan, Dongfang Zhao
2017 A* conf
Coordinating Filters for Faster Deep Neural Networks.
ICCV
Wei Wen, Cong Xu, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li
2017 J jnl
Coordinating Filters for Faster Deep Neural Networks.
CoRR
Wei Wen, Cong Xu, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li
2017 — conf
TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning.
NIPS
Wei Wen, Cong Xu, Feng Yan, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li
2017 J jnl
TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning.
CoRR
Wei Wen, Cong Xu, Feng Yan, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li
2016 J jnl
BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories.
J. Comput. Sci. Technol.
Jishen Zhao, Cong Xu, Tao Zhang, Yuan Xie
2016 A conf
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.
ICCAD
Shuangchen Li, Liu Liu, Peng Gu, Cong Xu, Yuan Xie
2016 A* conf
NVSim-VX
DAC
Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen
2016 A* conf
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
ISCA
Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie
2016 A* conf
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.
DAC
Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie
2015 A conf
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.
ICS
Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi
2015 J jnl
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.
ACM Trans. Design Autom. Electr. Syst.
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2015 J jnl
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.
IEEE Trans. Multi Scale Comput. Syst.
Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Yuan Xie
2015 J jnl
Memory and Storage System Design with Nonvolatile Memory Technologies.
Inf. Media Technol.
Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie
2015 J jnl
Memory and Storage System Design with Nonvolatile Memory Technologies.
IPSJ Trans. Syst. LSI Des. Methodol.
Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie
2015 — conf
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues.
ASP-DAC
Yang Zheng, Cong Xu, Yuan Xie
2015 A* conf
Overcoming the challenges of crossbar resistive memory architectures.
HPCA
Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
2014 — conf
3D-SWIFT: a high-performance 3D-stacked wide IO DRAM.
ACM Great Lakes Symposium on VLSI
Tao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie
2014 A* conf
Adaptive placement and migration policy for an STT-RAM-based hybrid cache.
HPCA
Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie
2014 A conf
Architecting 3D vertical resistive memory for next-generation storage systems.
ICCAD
Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014 — conf
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.
ISQED
Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie
2014 A* conf
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture.
HPCA
Tao Zhang, Matthew Poremba, Cong Xu, Guangyu Sun, Yuan Xie
2014 A* conf
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation.
ISCA
Tao Zhang, Ke Chen, Cong Xu, Guangyu Sun, Tao Wang, Yuan Xie
2014 — conf
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
ASP-DAC
Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie
2014 — conf
Reliability-aware cross-point resistive memory design.
ACM Great Lakes Symposium on VLSI
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014 — conf
TSV power supply array electromigration lifetime analysis in 3D ICS.
ACM Great Lakes Symposium on VLSI
Qiaosha Zou, Tao Zhang, Cong Xu, Yuan Xie
2014 A conf
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing.
ICCAD
Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie
2013 A conf
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.
ICCAD
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2013 C conf
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system.
ICCD
Tao Zhang, Cong Xu, Yuan Xie, Guangyu Sun
2013 C conf
Low power multi-level-cell resistive memory design with incomplete data mapping.
ICCD
Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie
2013 A* conf
Understanding the trade-offs in multi-level cell ReRAM memory design.
DAC
Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012 A* conf
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.
DAC
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das
2012 A conf
Design trade-offs for high density cross-point resistive memory.
ISLPED
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012 A conf
Modeling and design exploration of FBDRAM as on-chip memory.
DATE
Guangyu Sun, Cong Xu, Yuan Xie
2012 J jnl
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi
2012 — conf
When to forget: A system-level perspective on STT-RAMs.
ASP-DAC
Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan
2011 A conf
Bandwidth-aware reconfigurable cache design with hybrid memory technologies.
ICCAD
Jishen Zhao, Cong Xu, Yuan Xie
2011 A conf
Design implications of memristor-based RRAM cross-point structures.
DATE
Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2011 A conf
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.
ICCAD
Cong Xu, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Matt Nowak, Yuan Xie
2011 A* conf
Moguls: a model to explore the memory hierarchy for bandwidth improvements.
ISCA
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen
2010 A* conf
Impact of process variations on emerging memristor.
DAC
Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie