Cong Shi

58 papers A* 4C 2Journal 39Unranked 13
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 10 000-Inference/s Bio-Inspired Spiking Vision Chip Based on an End-to-End SNN Embedding Image Signal Enhancement.
IEEE J. Solid State Circuits
Xu Yang, Fuming Lei, Na Tian, Cong Shi, Zhe Wang, Shuangming Yu, Runjiang Dou, Peng Feng, Nan Qi, Zhongming Wei, Jian Liu, Kaiyou Wang, Nanjian Wu, Liyuan Liu
2025 J jnl
A Visual-Cortex-Mimetic Tiny Neuromorphic Vision Processor Based on Reconfigurable Cortical Neuron Unit.
IEEE Trans. Circuits Syst. II Express Briefs
Mingju Chen, Junxian He, Haibing Wang, Tengxiao Wang, Haoran Gao, Liyuan Liu, Ying Wang, Cong Shi
2025 J jnl
AM-CIM: Approximate Memory Based Near Sensor Compute-in-Memory Architecture for Keyword Spotting.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuhao Liu, Xiaotao Jia, Guangcai Yuan, Jianyi Yu, Cong Shi, Qi Wei, Youguang Zhang, Weisheng Zhao, Fei Qiao
2025 J jnl
An Edge Neuromorphic Processor With High-Accuracy On-Chip Aggregate-Label Learning.
IEEE Trans. Circuits Syst. II Express Briefs
Guanyu Chen, Mingju Chen, Tengxiao Wang, Haibing Wang, Xiang Fu, Yingcheng Lin, Liyuan Liu, Cong Shi
2025 J jnl
MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference.
IEEE Trans. Circuits Syst. II Express Briefs
Zhengqing Zhong, Haibing Wang, Mingju Chen, Yingcheng Lin, Min Tian, Tengxiao Wang, Liyuan Liu, Cong Shi
2025 J jnl
MorphBungee-Tiny: An Ultra-Low-Cost FPGA Implementation of Neuromorphic Architecture With High-Accuracy On-Chip E-Prop Learning.
IEEE Trans. Circuits Syst. II Express Briefs
Zhengqing Zhong, Jialin Yang, Haibing Wang, Ying Jiang, Yingcheng Lin, Ping Gan, Liyuan Liu, Liang Liang, Cong Shi
2025 J jnl
MorphBungee: A 65-nm 7.2-mm
IEEE Trans. Biomed. Circuits Syst.
Tengxiao Wang, Min Tian, Haibing Wang, Zhengqing Zhong, Junxian He, Fang Tang, Xichuan Zhou, Yingcheng Lin, Shuangming Yu, Liyuan Liu, Cong Shi
2025 J jnl
STOP: spatiotemporal orthogonal propagation for weight-threshold-leakage synergistic training of deep spiking neural networks.
Neuromorph. Comput. Eng.
Haoran Gao, Xichuan Zhou, Yingcheng Lin, Min Tian, Liyuan Liu, Cong Shi
2024 J jnl
A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap.
Siyuan Wei, Ke Ning, Lei Kang, Xuemin Zheng, Mingxin Zhao, Mengmeng Xu, Shuyu Wang, Xuanzhe Xu, Runjiang Dou, Shuangming Yu, Xu Yang, Jian Liu, Cong Shi, Nanjian Wu, Liyuan Liu
2024 J jnl
A visual cortex-inspired edge neuromorphic hardware architecture with on-chip multi-layer STDP learning.
Comput. Electr. Eng.
Junxian He, Min Tian, Ying Jiang, Haibing Wang, Tengxiao Wang, Xichuan Zhou, Liyuan Liu, Nanjian Wu, Ying Wang, Cong Shi
2024 J jnl
Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning.
IEEE Trans. Circuits Syst. II Express Briefs
Cong Shi, Xiang Fu, Haibing Wang, Yingcheng Lin, Ying Jiang, Liyuan Liu, Nanjian Wu, Min Tian
2024 J jnl
LLD-GAN: An end-to-end network for low-light image demosaicking.
Displays
Li Wang, Cong Shi, Shrinivas J. Pundlik, Xu Yang, Liyuan Liu, Gang Luo
2024 J jnl
STOP: Spatiotemporal Orthogonal Propagation for Weight-Threshold-Leakage Synergistic Training of Deep Spiking Neural Networks.
CoRR
Haoran Gao, Xichuan Zhou, Yingcheng Lin, Min Tian, Liyuan Liu, Cong Shi
2023 J jnl
A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods.
IEEE Trans. Circuits Syst. II Express Briefs
Lei Kang, Xu Yang, Chi Zhang, Shuangming Yu, Runjiang Dou, Wenchang Li, Cong Shi, Jian Liu, Nanjian Wu, Liyuan Liu
2023 — conf
A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors.
ICTA
Fuming Lei, Xu Yang, Jian Liu, Nanjian Wu, Cong Shi, Runjiang Dou, Liyuan Liu
2023 J jnl
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap.
Leyi Chen, Cong Shi, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Min Tian
2023 J jnl
An Edge Neuromorphic Hardware With Fast On-Chip Error-Triggered Learning on Compressive Sensed Spikes.
IEEE Trans. Circuits Syst. II Express Briefs
Cong Shi, Jingya Zhang, Tengxiao Wang, Zhengqing Zhong, Junxian He, Haoran Gao, Jianyi Yu, Ping Li, Min Tian
2023 J jnl
Learnable Leakage and Onset-Spiking Self-Attention in SNNs with Local Error Signals.
Sensors
Cong Shi, Li Wang, Haoran Gao, Min Tian
2023 — conf
Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip.
AICAS
Zhengqing Zhong, Tengxiao Wang, Haibing Wang, Zhihua Zhou, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi
2023 J jnl
Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests.
Sci. China Inf. Sci.
Cong Shi, Junxian He, Shrinivas J. Pundlik, Xichuan Zhou, Nanjian Wu, Gang Luo
2023 — conf
MorphBungee: A 65nm 7.2mm
A-SSCC
Tengxiao Wang, Min Tian, Zhengqing Zhong, Haibing Wang, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Nanjian Wu, Liyuan Liu, Cong Shi
2023 J jnl
Network Pruning for Bit-Serial Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiandong Zhao, Ying Wang, Cheng Liu, Cong Shi, Kaijie Tu, Lei Zhang
2022 C conf
A Lightweight Spiking GAN Model for Memristor-centric Silicon Circuit with On-chip Reinforcement Adversarial Learning.
ISCAS
Min Tian, Jing Lu, Haoran Gao, Haibing Wang, Jianyi Yu, Cong Shi
2022 J jnl
A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.
IEEE Trans. Circuits Syst. II Express Briefs
Zhen He, Cong Shi, Tengxiao Wang, Ying Wang, Min Tian, Xichuan Zhou, Ping Li, Liyuan Liu, Nanjian Wu, Gang Luo
2022 — conf
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.
APCCAS
Leyi Chen, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Cong Shi, Min Tian
2022 — conf
MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks.
BioCAS
Tengxiao Wang, Haibing Wang, Junxian He, Zhengqing Zhong, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi
2022 J jnl
TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity.
IEEE Trans. Biomed. Circuits Syst.
Haibing Wang, Zhen He, Tengxiao Wang, Junxian He, Xichuan Zhou, Ying Wang, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi
2021 J jnl
A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.
Sensors
Ling Zhang, Jing Yang, Cong Shi, Yingcheng Lin, Wei He, Xichuan Zhou, Xu Yang, Liyuan Liu, Nanjian Wu
2021 C conf
A Heterogeneous Spiking Neural Network for Computationally Efficient Face Recognition.
ISCAS
Xichuan Zhou, Zhenghua Zhou, Zhengqing Zhong, Jianyi Yu, Tengxiao Wang, Min Tian, Ying Jiang, Cong Shi
2021 J jnl
A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features.
IEEE Trans. Circuits Syst. II Express Briefs
Wei He, Jie Zhang, Yingcheng Lin, Xichuan Zhou, Ping Li, Liyuan Liu, Nanjian Wu, Cong Shi
2021 — conf
A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors.
ICTA
Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Liyuan Liu, Nanjian Wu, Cong Shi
2021 J jnl
An Edge 3D CNN Accelerator for Low-Power Activity Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ying Wang, Yongchen Wang, Cong Shi, Long Cheng, Huawei Li, Xiaowei Li
2021 J jnl
CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features.
Neurocomputing
Tengxiao Wang, Cong Shi, Xichuan Zhou, Yingcheng Lin, Junxian He, Ping Gan, Ping Li, Ying Wang, Liyuan Liu, Nanjian Wu, Gang Luo
2021 J jnl
DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Cong Shi, Tengxiao Wang, Junxian He, Jianghao Zhang, Liyuan Liu, Nanjian Wu
2021 — conf
Exploiting Memristors for Neuromorphic Reinforcement Learning.
AICAS
Cong Shi, Jing Lu, Ying Wang, Ping Li, Min Tian
2021 J jnl
Hapke Data Augmentation for Deep Learning-Based Hyperspectral Data Analysis With Limited Samples.
IEEE Geosci. Remote. Sens. Lett.
Kai Qin, Fangyuan Ge, Yingjun Zhao, Ling Zhu, Ming Li, Cong Shi, Dong Li, Xichuan Zhou
2021 A* conf
Optimizing Information Theory Based Bitwise Bottlenecks for Efficient Mixed-Precision Activation Quantization.
AAAI
Xichuan Zhou, Kui Liu, Cong Shi, Haijun Liu, Ji Liu
2021 — conf
TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning.
ICTA
Haibing Wang, Zhen He, Jinsong Rao, Tengxiao Wang, Junxian He, Min Tian, Xichuan Zhou, Liyuan Liu, Nanjian Wu, Cong Shi
2020 J jnl
A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification.
Sensors
Wei He, Jinguo Huang, Tengxiao Wang, Yingcheng Lin, Junxian He, Xichuan Zhou, Ping Li, Ying Wang, Nanjian Wu, Cong Shi
2020 — conf
A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution.
ICTA
Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Ying Jiang, Liyuan Liu, Nanjian Wu, Cong Shi
2020 A* conf
BitPruner: Network Pruning for Bit-serial Accelerators.
DAC
Xiandong Zhao, Ying Wang, Cheng Liu, Cong Shi, Kaijie Tu, Lei Zhang
2020 A* conf
MoNet3D: Towards Accurate Monocular 3D Object Localization in Real Time.
ICML
Xichuan Zhou, Yicong Peng, Chunqiao Long, Fengbo Ren, Cong Shi
2020 J jnl
MoNet3D: Towards Accurate Monocular 3D Object Localization in Real Time.
CoRR
Xichuan Zhou, Yicong Peng, Chunqiao Long, Fengbo Ren, Cong Shi
2020 J jnl
Neural Network Activation Quantization with Bitwise Information Bottlenecks.
CoRR
Xichuan Zhou, Kui Liu, Cong Shi, Haijun Liu, Ji Liu
2019 — conf
20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip.
ASICON
Junxian He, Xichuan Zhou, Yingcheng Lin, Chonglei Sun, Cong Shi, Nanjian Wu, Gang Luo
2019 J jnl
A Hardware-Friendly Optical Flow-Based Time-to-Collision Estimation Algorithm.
Sensors
Cong Shi, Zhuoran Dong, Shrinivas J. Pundlik, Gang Luo
2019 — conf
High-speed Classification of AER Data Based on a Low-cost Hardware System.
ASICON
Jinguo Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, Nanjian Wu, Gang Luo
2019 A* conf
Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis.
DAC
Yongchen Wang, Ying Wang, Huawei Li, Cong Shi, Xiaowei Li
2018 J jnl
A Compact VLSI System for Bio-Inspired Visual Motion Estimation.
IEEE Trans. Circuits Syst. Video Technol.
Cong Shi, Gang Luo
2018 J jnl
A Streaming Motion Magnification Core for Smart Image Sensors.
IEEE Trans. Circuits Syst. II Express Briefs
Cong Shi, Gang Luo
2018 J jnl
Exploiting Lightweight Statistical Learning for Event-Based Vision Processing.
IEEE Access
Cong Shi, Jiajun Li, Ying Wang, Gang Luo
2015 J jnl
A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor.
Sci. China Inf. Sci.
Yangfan Zhou, Zhongxiang Cao, Ye Han, Quanliang Li, Cong Shi, Runjiang Dou, Qi Qin, Jian Liu, Nanjian Wu
2014 — conf
7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network.
ISSCC
Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang
2014 J jnl
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network.
IEEE J. Solid State Circuits
Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang
2014 J jnl
A high speed 1000 fps CMOS image sensor with low noise global shutter pixels.
Sci. China Inf. Sci.
Yangfan Zhou, Zhongxiang Cao, Qi Qin, Quanliang Li, Cong Shi, Nanjian Wu
2014 J jnl
A high speed multi-level-parallel array processor for vision chips.
Sci. China Inf. Sci.
Cong Shi, Jie Yang, Nanjian Wu, Zhihua Wang
2014 J jnl
A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip.
Sci. China Inf. Sci.
Cong Shi, Jie Yang, Liyuan Liu, Nanjian Wu, Zhihua Wang
2013 — conf
A novel architecture of local memory for programmable SIMD vision chip.
ASICON
Zhe Chen, Jie Yang, Cong Shi, Nanjian Wu