Colin Yu Lin

19 papers A 1B 7Misc 2Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2021 J jnl
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weiyun Jiang, Kaiqi Zhang, Colin Yu Lin, Feng Xing, Zheng Zhang
2020 J jnl
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform.
CoRR
Weiyun Jiang, Kaiqi Zhang, Colin Yu Lin, Feng Xing, Zheng Zhang
2016 J jnl
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Jia, Hai-Gang Yang, Colin Yu Lin, Rui Chen, Xin-Gang Wang, Zhenhong Guo
2016 J jnl
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels.
SIGARCH Comput. Archit. News
Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang
2015 B conf
A technology mapper for depth-constrained FPGA logic cells.
FPL
Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne
2014 B conf
A semi-supervised modeling approach for performance characterization of FPGA architectures.
FPL
Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin
2014 B conf
A survey of open source processors for FPGAs.
FPL
Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao, Haigang Yang
2014 B conf
Exploring architecture parameters for dual-output LUT based FPGAs.
FPL
Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang
2014 — conf
Size aware placement for island style FPGAs.
FPT
JunYing Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang
2013 Misc conf
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency.
FCCM
Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So
2013 J jnl
Design space exploration for sparse matrix-matrix multiplication on FPGAs.
Int. J. Circuit Theory Appl.
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
2013 B conf
Timing-constrained minimum area/power FPGA memory mapping.
FPL
Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang
2012 J jnl
Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis.
SIGARCH Comput. Archit. News
Colin Yu Lin, Hayden Kwok-Hay So
2012 A conf
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only).
FPGA
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
2011 B conf
A Model for Matrix Multiplication Performance on FPGAs.
FPL
Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong
2011 Misc conf
A Model for Peak Matrix Performance on FPGAs.
FCCM
Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong
2010 — conf
Design space exploration for sparse matrix-matrix multiplication on FPGAs.
FPT
Colin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So
2009 B conf
Operation scheduling for FPGA-based reconfigurable computers.
FPL
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
2008 — conf
A Network Based Functional Verification Method of IEEE 1394a PHY Core.
ISVLSI
Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan