Colin Weltin-Wu

16 papers Journal 10Unranked 6
YearRankTypeTitle / Venue / Authors
2024 J jnl
A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Amr I. Eissa, Enrique Alvarez-Fontecilla, Colin Weltin-Wu, Ian Galton
2021 J jnl
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Enrique Alvarez-Fontecilla, Amr I. Eissa, Eslam Helal, Colin Weltin-Wu, Ian Galton
2019 J jnl
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ian Galton, Colin Weltin-Wu
2015 — conf
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation.
ISSCC
Colin Weltin-Wu, Guobi Zhao, Ian Galton
2015 J jnl
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion.
IEEE J. Solid State Circuits
Colin Weltin-Wu, Guobi Zhao, Ian Galton
2015 J jnl
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Colin Weltin-Wu, Eythan Familier, Ian Galton
2013 J jnl
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution.
IEEE J. Solid State Circuits
Colin Weltin-Wu, Yannis P. Tsividis
2012 — conf
An event-driven, alias-free ADC with signal-dependent resolution.
VLSIC
Colin Weltin-Wu, Yannis P. Tsividis
2012 J jnl
Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation.
IEEE J. Solid State Circuits
Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis
2011 — conf
GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity.
ISSCC
Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis
2010 J jnl
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation.
IEEE J. Solid State Circuits
Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, Francesco Svelto
2010 — conf
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation.
ISSCC
Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Marco Cusmai, Francesco Svelto
2010 J jnl
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Colin Weltin-Wu, Enrico Temporiti, Marco Cusmai, Daniele Baldi, Francesco Svelto
2009 J jnl
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques.
IEEE J. Solid State Circuits
Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto
2009 — conf
Insights into wideband fractional All-Digital PLLs for RF applications.
CICC
Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto
2008 — conf
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction.
ISSCC
Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Francesco Svelto