Cliff C. N. Sze

51 papers A* 8A 6Misc 1Journal 12Unranked 20

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	Fast and Highly Scalable Bayesian MDP on a GPU Platform. BCB He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu, Cliff C. N. Sze
2017	J	`jnl`	Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. IPSJ Trans. Syst. LSI Des. Methodol. Johann Knechtel, Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze
2016	—	`conf`	Cell Selection for High-Performance Designs in an Industrial Design Flow. ISPD Tiago J. Reimann, Cliff C. N. Sze, Ricardo Reis
2016	J	`jnl`	Challenges of cell selection algorithms in industrial high performance microprocessor designs. Integr. Tiago Reimann, Cliff C. N. Sze, Ricardo Reis
2016	—	`conf`	GPU acceleration for Bayesian control of Markovian genetic regulatory networks. BHI He Zhou, Jiang Hu, Sunil P. Khatri, Frank Liu, Cliff C. N. Sze, Mohammadmahdi R. Yousefi
2015	—	`conf`	Gate sizing and threshold voltage assignment for high performance microprocessor designs. ASP-DAC Tiago Reimann, Cliff C. N. Sze, Ricardo Reis
2015	J	`jnl`	Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze
2014	—	`ed.`	International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014 ISPD Cliff C. N. Sze, Azadeh Davoodi
2014	—	`conf`	Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze
2014	J	`jnl`	Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2013	A	`conf`	CATALYST: planning layer directives for effective design closure. DATE Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar
2013	A	`conf`	Clock power minimization using structured latch templates and decision tree induction. ICCAD Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan
2013	Misc	`conf`	Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo. ICCS Thomas H. Osiecki, Min-Yu Tsai, Anne E. Gattiker, Damir A. Jamsek, Sani R. Nassif, William Evan Speight, Cliff C. N. Sze
2013	—	`conf`	ISPD 2013 expert designer/user session (eds). ISPD Cliff C. N. Sze, Laleh Behjat, Nikhil Jayakumar, Atul Walimbe, Gregory Ford, Mark Zwolinski, Harish Dangat, Giriraj Kakol
2013	—	`ed.`	International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013 ISPD Cheng-Kok Koh, Cliff C. N. Sze
2013	—	`conf`	Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
2013	A*	`conf`	Routing congestion estimation with real design constraints. DAC Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan
2012	A*	`conf`	GLARE: global and local wiring aware routability evaluation. DAC Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2012	A*	`conf`	Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou
2012	A	`conf`	ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
2012	J	`jnl`	Postgrid Clock Routing for High Performance Microprocessor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
2012	A*	`conf`	The DAC 2012 routability-driven placement contest and benchmark suite. DAC Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
2012	—	`conf`	WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
2011	J	`jnl`	Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
2011	—	`conf`	Grid-to-ports clock routing for high performance microprocessor designs. ISPD Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
2011	J	`jnl`	Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov
2011	—	`conf`	The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy
2011	A	`conf`	The future of clock network synthesis. ICCAD Cliff C. N. Sze
2010	—	`conf`	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. ISPD Cliff C. N. Sze
2010	—	`conf`	Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou
2008	—	`ch.`	Buffering in the Layout Environment. Handbook of Algorithms for Physical Design Automation Jiang Hu, Cliff C. N. Sze
2008	—	`conf`	The ISPD global routing benchmark suite. ISPD Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz
2008	—	`ch.`	Timing-Driven Interconnect Synthesis. Handbook of Algorithms for Physical Design Automation Jiang Hu, Gabriel Robins, Cliff C. N. Sze
2007	J	`jnl`	Techniques for Fast Physical Synthesis. Proc. IEEE Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2007	—	`conf`	The nuts and bolts of physical synthesis. SLIP Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2006	J	`jnl`	Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2006	A*	`conf`	Fast algorithms for slew constrained minimum cost buffering. DAC Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
2006	A	`conf`	Integrated placement and skew optimization for rotary clocking. DATE Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
2006	A*	`conf`	Timing-driven Steiner trees are (practically) free. DAC Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
2005	—	`conf`	Making fast buffer insertion even faster via approximation techniques. ASP-DAC Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2005	A*	`conf`	Navigating registers in placement for clock network minimization. DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	A*	`conf`	Path based buffer insertion. DAC Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2005	—	`conf`	Register placement for low power clock network. ASP-DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	—	`conf`	Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
2004	—	`conf`	A place and route aware buffered Steiner tree construction. ASP-DAC Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
2004	A	`conf`	Accurate estimation of global buffer delay within a floorplan. ICCAD Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2004	J	`jnl`	Multilevel circuit clustering for delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
2004	J	`jnl`	Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
2003	J	`jnl`	Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cliff C. N. Sze, Ting-Chi Wang
2002	—	`conf`	Multi-Level Circuit Clustering for Delay Minimization. IWLS Cliff C. N. Sze, Ting-Chi Wang
2002	—	`conf`	Optimal circuit clustering with variable interconnect delay. ISCAS (4) Cliff C. N. Sze, Ting-Chi Wang