Claudio Nani - RankMe

20 papers A 1C 1Journal 7Unranked 11

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	23.2 A 2-Channel 800Gb/s Transceiver for Coherent-Lite Applications with <300ns Latency in 5nm FinFET. ISSCC Marco Sosio, Claudio Nani, Enrico Monaco, Nicola Ghittori, Domenico Albano, Alessio Di Pasquo, Alessandro Bosi, Travis Lovitt, Gabriele Gira, Fulvio Martinelli, Victor Karam, Devrishi Khanna, Mehdi N. Khiarak, Sasan Cyrusian, Mehdi Davoodi, Marco Garampazzi, Nimesh N. Miral, Fabio Giunco, Ivan Fabiano, Nicola Codega, Claudio Asero, Leonardo Daniel Herbas Burgos, Enrico Temporiti, Shawn Scouten, Kishore Kota, Yang Fu, Ruibin Jin, Josef Mueller, Michael Leung, Arash Farhoodfar, Stephen Jantzi, Ken Chang
2025	J	`jnl`	A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz. IEEE J. Solid State Circuits Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi
2025	J	`jnl`	An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. IEEE J. Solid State Circuits Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, Domenico Albano, Claudio Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, Leonardo Daniel Herbas Burgos, Stanley S. K. Ho, Enrico Monaco, Benjamín T. Reyes, Paolo Rossi, Enrico Temporiti, Paolo Pascale, Fernando De Bernardinis, Shawn Scouten, Stephen Jantzi
2024	—	`conf`	18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm. ISSCC F. Ahmad, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, Fredy Solis, Gabriele Minoia, Geoff Hatcher, Hugo S. Carrer, K. Kota, L. Wang, M. Bachu, Marco Garampazzi, M. Hassanpourghadi, N. Fan, P. Prabha, R. L. Nguyen, S. Ho, T. Dusatko, T. Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse
2024	—	`conf`	18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET. ISSCC R. L. Nguyen, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, F. Ahmad, Fredy Solis, Gabriele Minoia, Geoff Hatcher, M. Bachu, Marco Garampazzi, Mohsen Hassanpourghadi, N. Fan, P. Prabha, S. Fan, S. Ho, T. Dusatko, Tzu-Fan Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse
2024	—	`conf`	A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. VLSI Technology and Circuits Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi
2024	—	`conf`	A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. VLSI Technology and Circuits Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, D. Albano, C. Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, D. Herbas, S. Ho, Enrico Monaco, Benjamín T. Reyes, P. Rossi, E. Temporiti, P. Pascale, Fernando De Bernardinis, S. Scouten, S. Jantzi
2023	—	`conf`	A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm Technology. ApplePies Valentina Marazzi, Enrico Monaco, Claudio Nani, Danilo Manstretta
2023	—	`conf`	Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET Technology. PRIME Valentina Marazzi, Enrico Monaco, Claudio Nani, Danilo Manstretta
2021	C	`conf`	A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC. ISCAS Alessio Di Pasquo, Claudio Nani, Enrico Monaco, Luca Fanucci
2021	—	`conf`	Delay-lines jitter modeling and efficiency analysis in FinFET technology. ICECS Alessio Di Pasquo, Enrico Monaco, Claudio Nani, Luca Fanucci
2020	J	`jnl`	A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. IEEE J. Solid State Circuits Matteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani
2019	—	`conf`	A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. ISSCC Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti
2016	—	`conf`	27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS. ISSCC Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani
2016	J	`jnl`	A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS. IEEE J. Solid State Circuits Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani
2012	J	`jnl`	A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas
2011	J	`jnl`	A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. IEEE J. Solid State Circuits Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard van der Weide
2011	—	`conf`	A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. ISSCC Konstantinos Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard van der Weide
2009	J	`jnl`	Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters. IEICE Trans. Electron. Sergio Saponara, Pierluigi Nuzzo, Claudio Nani, Geert Van der Plas, Luca Fanucci
2008	A	`conf`	Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. DATE Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas