Claudia Feregrino

14 papers A 1B 2C 1Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2021 J jnl
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks.
J. Sensors
Miguel Morales-Sandoval, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo
2019 — ed.
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019
ReConFig
David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner
2019 J jnl
Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology.
J. Parallel Distributed Comput.
René Cumplido, Maya B. Gokhale, Claudia Feregrino, Michael Hübner
2018 — ed.
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018
ReConFig
David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt
2016 — ed.
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016
ReConFig
Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass
2015 — conf
Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware.
NFMCP
Lázaro Bustio, René Cumplido, Raudel Hernández-León, José Manuel Bande Serrano, Claudia Feregrino
2012 J jnl
A multi-cycle fixed point square root module for FPGAs.
IEICE Electron. Express
Fernando Martin del Campo, Alicia Morales-Reyes, Roberto Perez-Andrade, René Cumplido, Aldo G. Orozco-Lugo, Claudia Feregrino
2012 J jnl
Hardware-software platform for computing irreducible testors.
Expert Syst. Appl.
Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino, José Francisco Martínez Trinidad
2012 J jnl
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10).
Int. J. Reconfigurable Comput.
Claudia Feregrino, Miguel Arias, Kris Gaj, Viktor K. Prasanna, Marco D. Santambrogio, Ron Sass
2006 C conf
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification.
CIARP
René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino
2001 B conf
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding.
FPL
Riad Stefo, José Luis Núñez, Claudia Feregrino, Sudipta Mahapatra, Simon R. Jones
2001 B conf
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor.
FPL
José Luis Núñez, Claudia Feregrino, Simon R. Jones, Stephen Bateman
1999 — conf
The X-MatchLITE FPGA-Based Data Compressor.
EUROMICRO
José Luis Núñez, Claudia Feregrino, Simon R. Jones, Stephen Bateman
1999 A conf
The X-MatchLITE FPGA-Based Data Compressor.
FPGA
José Luis Núñez, Claudia Feregrino, Stephen Bateman, Simon R. Jones