Claude Thibeault

105 papers A 3B 1C 7Misc 15Journal 49Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Statistical Performance Analysis Framework for Bundled-Data Asynchronous Circuits With Dynamic Voltage Scaling. IET Comput. Digit. Tech. Maryem Benyoussef, Claude Thibeault, Yvon Savaria
2023	J	`jnl`	Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Simon Pichette, Claude Thibeault
2021	J	`jnl`	Introducing KeyRing self-timed microarchitecture and timing-driven design flow. IET Comput. Digit. Tech. Mickaël Fiorentino, Claude Thibeault, Yvon Savaria
2020	J	`jnl`	Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. IEEE Trans. Very Large Scale Integr. Syst. Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2019	C	`conf`	A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. ISCAS Maryem Benyoussef, Claude Thibeault, Yvon Savaria
2019	—	`conf`	AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology. ASYNC Mickaël Fiorentino, Claude Thibeault, Yvon Savaria, François Gagnon, Tom Awad, Doug Morrissey, Michel Laurence
2019	J	`jnl`	Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. J. Electron. Test. Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2018	Misc	`conf`	Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. VTS Omar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria, Claude Thibeault
2018	J	`jnl`	Fast Low-Complexity Decoders for Low-Rate Polar Codes. J. Signal Process. Syst. Pascal Giard, Alexios Balatsoukas-Stimming, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2018	J	`jnl`	Low-Latency Software Polar Decoders. J. Signal Process. Syst. Pascal Giard, Gabi Sarkis, Camille Leroux, Claude Thibeault, Warren J. Gross
2018	J	`jnl`	On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques. IEEE Trans. Very Large Scale Integr. Syst. Claude Thibeault, Ghyslain Gagnon
2017	J	`jnl`	A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code. CoRR Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
2017	Misc	`conf`	A new delay testing signal scheme robust to power distribution network impedance variation. VTS Claude Thibeault, Ali Louati
2017	—	`conf`	FPGA implementation of Token-based Self-timed processors: A case study. NEWCAS Mickaël Fiorentino, Yvon Savaria, Claude Thibeault
2017	—	`book`	High-Speed Decoders for Polar Codes Pascal Giard, Claude Thibeault, Warren J. Gross
2017	J	`jnl`	PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. CoRR Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
2017	J	`jnl`	PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. IEEE J. Emerg. Sel. Topics Circuits Syst. Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
2016	Misc	`conf`	A multi-Gbps unrolled hardware list decoder for a systematic polar code. ACSSC Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
2016	C	`conf`	A practical design method for prototyping self-timed processors using FPGAs. ISCAS Mickaël Fiorentino, Yvon Savaria, Claude Thibeault, Pascal Gervais
2016	J	`jnl`	Design of a tolerant flight control system in response to multiple actuator control signal faults induced by cosmic rays. IEEE Trans. Aerosp. Electron. Syst. Azeddine Ghodbane, Maarouf Saad, Christelle Hobeika, Jean-François Boland, Claude Thibeault
2016	—	`conf`	Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA. CCECE Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria
2016	—	`ch.`	Efficient identification of Faces in video Streams using low-Power Multi-Core Devices. Handbook of Pattern Recognition and Computer Vision Donavan Prieur, Eric Granger, Yvon Savaria, Claude Thibeault
2016	J	`jnl`	Fast List Decoders for Polar Codes. IEEE J. Sel. Areas Commun. Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2016	J	`jnl`	Fast Low-Complexity Decoders for Low-Rate Polar Codes. CoRR Pascal Giard, Alexios Balatsoukas-Stimming, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2016	J	`jnl`	Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes. IEEE Trans. Commun. Gabi Sarkis, Ido Tal, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2016	J	`jnl`	Hardware Decoders for Polar Codes: An Overview. CoRR Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Burg, Claude Thibeault, Warren J. Gross
2016	C	`conf`	Hardware decoders for polar codes: An overview. ISCAS Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Peter Burg, Claude Thibeault, Warren J. Gross
2016	J	`jnl`	Multi-Mode Unrolled Architectures for Polar Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2016	Misc	`conf`	Partitioned successive-cancellation list decoding of polar codes. ICASSP Seyyed Ali Hashemi, Alexios Balatsoukas-Stimming, Pascal Giard, Claude Thibeault, Warren J. Gross
2016	J	`jnl`	Towards an efficient SEU effects emulation on SRAM-based FPGAs. Microelectron. Reliab. Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
2016	Misc	`conf`	WeSPer: A flexible small delay defect quality metric. VTS Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2015	—	`conf`	A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs. SiPS Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2015	—	`conf`	A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline. ASYNC Louis-Charles Trudeau, Ghyslain Gagnon, François Gagnon, Claude Thibeault, Thomas Awad, Doug Morrissey
2015	—	`conf`	An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs. EWDTS Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
2015	J	`jnl`	Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation. CoRR Mostafa Darvishi, Yves Audet, Yves Blaquière, Claude Thibeault
2015	J	`jnl`	Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes. CoRR Gabi Sarkis, Ido Tal, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2015	Misc	`conf`	Foreword. VTS Claude Thibeault
2015	J	`jnl`	Functional Constraint Extraction From Register Transfer Level for ATPG. IEEE Trans. Very Large Scale Integr. Syst. Christelle Hobeika, Claude Thibeault, Jean-François Boland
2015	J	`jnl`	Low-Latency Software Polar Decoders. CoRR Pascal Giard, Gabi Sarkis, Camille Leroux, Claude Thibeault, Warren J. Gross
2015	C	`conf`	Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. IOLTS Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
2015	J	`jnl`	Partitioned Successive-Cancellation List Decoding of Polar Codes. CoRR Seyyed Ali Hashemi, Alexios Balatsoukas-Stimming, Pascal Giard, Claude Thibeault, Warren J. Gross
2015	—	`conf`	Self-timed circuits FPGA implementation flow. NEWCAS Mickaël Fiorentino, Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2015	J	`jnl`	Unrolled Polar Decoders, Part I: Hardware Architectures. CoRR Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2015	J	`jnl`	Unrolled Polar Decoders, Part II: Fast List Decoders. CoRR Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2014	J	`jnl`	A 237 Gbps Unrolled Hardware Polar Decoder. CoRR Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2014	—	`conf`	Autogenerating software polar decoders. GlobalSIP Gabi Sarkis, Pascal Giard, Claude Thibeault, Warren J. Gross
2014	J	`jnl`	Fast Polar Decoders: Algorithm and Implementation. IEEE J. Sel. Areas Commun. Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2014	Misc	`conf`	Fast software polar decoders. ICASSP Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2014	J	`jnl`	Increasing the Speed of Polar List Decoders. CoRR Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2014	—	`conf`	Increasing the speed of polar list decoders. SiPS Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2014	C	`conf`	Multi-abstraction level signature generation and comparison based on radiation single event upset. IOLTS Christelle Hobeika, Simon Pichette, M. A. Leonard, Claude Thibeault, Jean-François Boland, Yves Audet
2014	J	`jnl`	On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations. CoRR Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria, Simon Pichette, Yves Audet
2014	C	`conf`	Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. MEMOCODE Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria, Claude Thibeault
2013	—	`conf`	A 0.35∼6.25 GHz cognitive radio frequency synthesizer architecture. MWSCAS Zakaria El Alaoui Ismaili, Frederic Nabki, Wessam Ajib, Claude Thibeault
2013	J	`jnl`	A Fast Software Polar Decoder. CoRR Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross
2013	J	`jnl`	A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design. J. Electron. Test. Claude Thibeault, Yassine Hariri, Syed Rafay Hasan, Christelle Hobeika, Yvon Savaria, Yves Audet, Fatima Zahra Tazi
2013	—	`conf`	A methodology for system-level fault injection based on gate-level faulty behavior. NEWCAS R. Robache, Jean-François Boland, Claude Thibeault, Yvon Savaria
2013	—	`conf`	Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking. FTSCS Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria, Claude Thibeault
2013	J	`jnl`	Fast Polar Decoders: Algorithm and Implementation. CoRR Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2013	J	`jnl`	Multi-User Multi-Carrier Differential Chaos Shift Keying Communication System CoRR Georges Kaddoum, Francois-Dominique Richardson, Sarra Adouni, François Gagnon, Claude Thibeault
2013	B	`conf`	Multi-user Multi-Carrier Differential Chaos Shift Keying communication system. IWCMC Georges Kaddoum, Francois-Dominique Richardson, Sarra Adouni, François Gagnon, Claude Thibeault
2013	J	`jnl`	Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG. CoRR Christelle Hobeika, Claude Thibeault, Jean-François Boland
2012	—	`conf`	An LPI design for secure OFDM systems. MILCOM Marwen Bouanen, François Gagnon, Georges Kaddoum, Denis Couillard, Claude Thibeault
2012	C	`conf`	FPGA implementation and evaluation of discrete-time chaotic generators circuits. IECON Pascal Giard, Georges Kaddoum, François Gagnon, Claude Thibeault
2012	—	`conf`	Fault tolerant flight control system using emmae method and reconfiguration with sliding mode technique. CCECE Azeddine Ghodbane, Maarouf Saad, Jean-François Boland, Claude Thibeault
2012	—	`conf`	High-throughput LDPC decoding using the RHS algorithm. DASIP François Leduc-Primeau, Alexandre J. Raymond, Pascal Giard, Kevin Cushon, Claude Thibeault, Warren J. Gross
2012	J	`jnl`	Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors. J. Electron. Test. Claude Thibeault, Yassine Hariri, Christelle Hobeika
2011	J	`jnl`	CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. Claude Thibeault, Yassine Hariri
2011	J	`jnl`	Leveraging green communications for carbon emission reductions: Techniques, testbeds, and emerging carbon footprint standards. IEEE Commun. Mag. Charles L. Despins, Fabrice Labeau, Tho Le-Ngoc, Richard Labelle, Mohamed Cheriet, Claude Thibeault, François Gagnon, Alberto Leon-Garcia, Omar Cherkaoui, Bill St. Arnaud, Jacques Mcneill, Yves Lemieux, Mathieu Lemay
2011	—	`conf`	Low complexity low power non-recursive digital filters with unconstrained topology. ECCTD Marc Joliveau, Michel Gendreau, François Gagnon, Claude Thibeault
2011	—	`conf`	Testing for Parasitic Memory Effect in SRAMs. Asian Test Symposium Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Claude Thibeault
2009	J	`jnl`	From synchronous to GALS: A new architecture for FPGAs. Microelectron. J. René Gagné, Jean Belzile, Claude Thibeault
2007	J	`jnl`	Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors. IET Comput. Digit. Tech. Yassine Hariri, Claude Thibeault
2007	Misc	`conf`	On a New Outlier Rejection Technique. VTS Claude Thibeault
2004	Misc	`conf`	On New Current Signatures and Adaptive Test Technique Combination. VTS Claude Thibeault
2003	—	`conf`	3DSDM: A 3 Data-Source Diagnostic Method. DFT Yassine Hariri, Claude Thibeault
2003	J	`jnl`	On Faster J. Electron. Test. Claude Thibeault
2003	J	`jnl`	Replacing J. Electron. Test. Claude Thibeault
2002	Misc	`conf`	Speeding-Up IDDQ Measurements. VTS Claude Thibeault
2002	—	`conf`	Yield Modeling of a WSI Telecom Router Architecture. DFT Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault
2001	Misc	`conf`	Tools for the Characterization of Bipolar CML Testability. VTS Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst
2000	J	`jnl`	Diagnosis Method Using DeltaIDDQ Probabilistic Signatures: Theory and Results. J. Electron. Test. Claude Thibeault
2000	Misc	`conf`	Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. VTS Claude Thibeault
2000	A	`conf`	Improving Delta-I_DDQ-based test methods. ITC Claude Thibeault
2000	J	`jnl`	On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults. IEEE Trans. Computers Claude Thibeault
1999	J	`jnl`	A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations. IEEE Trans. Computers Claude Thibeault, Guy Bégin
1999	A	`conf`	An histogram based procedure for current testing of active defects. ITC Claude Thibeault
1999	Misc	`conf`	On the Comparison of IDDQ and IDDQ Testing. VTS Claude Thibeault
1998	A	`conf`	Diagnosis method based on ΔIddq probabilistic signatures: experimental results. ITC Claude Thibeault, Luc Boisvert
1998	—	`conf`	Increasing Current Testing Resolution. DFT Claude Thibeault
1998	—	`conf`	On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. DFT Claude Thibeault, Luc Boisvert
1997	—	`conf`	A Cost Model for VLSI / MCM Systems. DFT Michel Kafrouni, Claude Thibeault, Yvon Savaria
1997	Misc	`conf`	A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. VTS Claude Thibeault
1997	—	`conf`	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. DFT Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault
1996	—	`conf`	Experimental Results from Iddf Testing. DFT Claude Thibeault, A. Payeur
1996	J	`jnl`	Panel Summaries. IEEE Des. Test Comput. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
1995	Misc	`conf`	Detection and location of faults and defects using digital signal processing. VTS Claude Thibeault
1995	J	`jnl`	Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. IEEE Trans. Computers Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1995	—	`conf`	FFT-based test of a yield monitor circuit. DFT Claude Thibeault, A. Payeur
1994	J	`jnl`	A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. IEEE Trans. Computers Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1994	—	`conf`	Using Fourier Analysis to Enhance IC Testability. DFT Claude Thibeault
1993	—	`conf`	Some Results on Yield and Local Design Rule Relaxation. DFT J. Crépeau, Claude Thibeault, Yvon Savaria
1992	J	`jnl`	Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits. J. Circuits Syst. Comput. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1992	J	`jnl`	Test quality of hierarchical defect-tolerant integrated circuits. J. Electron. Test. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1990	—	`conf`	Impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits. FTCS Claude Thibeault, Jean-Louis Houle