Claude Chappert

33 papers A 1B 2C 5Journal 12Unranked 13

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. ACM J. Emerg. Technol. Comput. Syst. Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao
2015	J	`jnl`	Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. Wang Kang, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014	—	`conf`	An overview of spin-based integrated circuits. ASP-DAC Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014	J	`jnl`	Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert
2014	B	`conf`	Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture. IJCNN Zhaohao Wang, Weisheng Zhao, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Claude Chappert
2014	A	`conf`	Spintronics for low-power computing. DATE Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014	J	`jnl`	Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. Circuits Syst. I Regul. Pap. Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert
2014	J	`jnl`	Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms. IEEE Trans. Circuits Syst. I Regul. Pap. Djaafar Chabi, Weisheng Zhao, Erya Deng, Yue Zhang, Nesrine Ben Romdhane, Jacques-Olivier Klein, Claude Chappert
2013	J	`jnl`	A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. Microelectron. Reliab. Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona
2013	—	`conf`	Analytical study of complementary memristive synchronous logic gates. NANOARCH Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao
2013	—	`conf`	Emerging hybrid logic circuits based on non-volatile magnetic memories. NEWCAS Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona
2013	—	`conf`	Low power magnetic flip-flop based on checkpointing and self-enable mechanism. NEWCAS Djaafar Chabi, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Claude Chappert
2013	J	`jnl`	Magnetic Adder Based on Racetrack Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein, Yue Zhang, Dafine Ravelosona, Claude Chappert
2013	C	`conf`	Spin-electronics based logic fabrics. VLSI-SoC Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert
2013	—	`conf`	Synchronous full-adder based on complementary resistive switching memory cells. NEWCAS Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012	J	`jnl`	Cross-point architecture for spin transfer torque magnetic random access memory CoRR Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2012	—	`conf`	Crossbar architecture based on 2R complementary resistive switching memory cell. NANOARCH Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012	J	`jnl`	Failure and reliability analysis of STT-MRAM. Microelectron. Reliab. Weisheng Zhao, Yue Zhang, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer
2012	C	`conf`	MRAM crossbar based configurable logic block. ISCAS Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert
2012	C	`conf`	Nanodevice-based novel computing paradigms and the neuromorphic approach. ISCAS Weisheng Zhao, Damien Querlioz, Jacques-Olivier Klein, Djaafar Chabi, Claude Chappert
2011	J	`jnl`	Design considerations and strategies for high-reliable STT-MRAM. Microelectron. Reliab. Weisheng Zhao, Thibaut Devolder, Yahya Lakys, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2011	—	`conf`	Design of MRAM based logic circuits and its applications. ACM Great Lakes Symposium on VLSI Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitorio Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert
2011	C	`conf`	Embedded MRAM for high-speed computing. VLSI-SoC Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli
2011	—	`conf`	High Performance SoC Design Using Magnetic Logic and Memory. VLSI-SoC (Selected Papers) Weisheng Zhao, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert
2011	—	`conf`	Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power. ARC Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert
2010	—	`conf`	Design of embedded MRAM macros for memory-in-logic applications. ACM Great Lakes Symposium on VLSI Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2010	B	`conf`	High Density Asynchronous LUT Based on Non-volatile MRAM Technology. FPL Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2009	J	`jnl`	Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit. ACM Trans. Embed. Comput. Syst. Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer
2009	J	`jnl`	TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ACM Trans. Reconfigurable Technol. Syst. Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat
2008	—	`conf`	Injection locked CMOS buffer dedicated to nanomagnetic based voltage controlled oscillator. ICECS Franck Badets, Lieven Lagae, Sven Cornelissen, Thibaut Devolder, Claude Chappert
2008	—	`conf`	Spintronic Device Based Non-volatile Low Standby Power SRAM. ISVLSI Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer
2007	C	`conf`	Synthesis of Finite State Machines with Magnetic Domain Wall Logic. ISCAS Jacques-Olivier Klein, Eric Belhaire, Claude Chappert, Florent Ouchet, Russell Cowburn, Dan Read, Dorothee Petit
2007	—	`conf`	TAS-MRAM based Non-volatile FPGA logic circuit. FPT Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert