Ckristian Duran

30 papers C 7Journal 16Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	CMOS Implementation of Field Programmable Spiking Neural Network for Hardware Reservoir Computing. CoRR Ckristian Duran, Nanako Kimura, Zolboo Byambadorj, Tetsuya Iizuka
2025	J	`jnl`	Fully-Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R-Based Layout Automation Framework. IEEE Access Shuowei Li, Ckristian Duran, Ritaro Takenaka, Tetsuya Iizuka
2025	J	`jnl`	Hardware-friendly implementation of physical reservoir computing with CMOS-based time-domain analog spiking neurons. Neuromorph. Comput. Eng. Nanako Kimura, Ckristian Duran, Zolboo Byambadorj, Ryosho Nakane, Tetsuya Iizuka
2024	C	`conf`	A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. ISCAS Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham
2024	J	`jnl`	Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons. CoRR Nanako Kimura, Ckristian Duran, Zolboo Byambadorj, Ryosho Nakane, Tetsuya Iizuka
2023	C	`conf`	In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. ISCAS Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham
2022	J	`jnl`	A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration. IEEE Trans. Circuits Syst. II Express Briefs Ckristian Duran, Elkim Roa
2022	—	`conf`	A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. ISOCC Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Trong-Thuc Hoang, Cong-Kha Pham
2022	J	`jnl`	A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse. IEEE Access Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2022	J	`jnl`	A Unified NVRAM and TRNG in Standard CMOS Technology. IEEE Access Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Cong-Kha Pham
2022	J	`jnl`	A Unified PUF and Crypto Core Exploiting the Metastability in Latches. Future Internet Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham
2022	J	`jnl`	ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. Cryptogr. Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Cong-Kha Pham, Trong-Thuc Hoang
2022	J	`jnl`	Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Ronaldo Serrano, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham
2022	J	`jnl`	Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling. IEEE Access Trong-Thuc Hoang, Ckristian Duran, Ronaldo Serrano, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2021	J	`jnl`	A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse. IEEE Access Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2021	—	`conf`	A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. ISOCC Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham
2021	J	`jnl`	A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Trong-Thuc Hoang, Ronaldo Serrano, Van-Phuc Hoang, Xuan-Tu Tran, Koichiro Ishibashi, Cong-Kha Pham
2021	C	`conf`	AES Sbox Acceleration Schemes for Low-Cost SoCs. ISCAS Ckristian Duran, Héctor Gómez, Elkim Roa
2021	—	`conf`	ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. ISOCC Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2021	C	`conf`	Routing-Aware Standard Cell Placement Algorithm Applying Boolean Satisfiability. ISCAS Ckristian Duran, Elkim Roa
2021	—	`conf`	System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture. HCS Trong-Thuc Hoang, Ckristian Duran, Ronaldo Serrano, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2020	—	`conf`	An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications. CICC Ckristian Duran, Megan Wachs, Luis E. Rueda G., Albert Huntington, Javier Ardila, Jack Kang, Andres Amaya, Héctor Gómez, Juan Romero, Laude Fernandez, Felipe Flechas, Rolando Torres, Juan Sebastian Moya, Wilmer Ramirez, Julian Arenas, Juan Gomez, Hanssel Morales, Camilo Rojas, Alex Mantilla, Elkim Roa, Krste Asanovic
2020	C	`conf`	Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors. ISCAS Trong-Thuc Hoang, Ckristian Duran, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2020	J	`jnl`	Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). IEICE Electron. Express Trong-Thuc Hoang, Ckristian Duran, Khai-Duy Nguyen, Tuan-Kiet Dang, Quynh Nguyen Quang Nhu, Phuc Hong Than, Xuan-Tu Tran, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2020	J	`jnl`	Quick Boot of Trusted Execution Environment With Hardware Accelerators. IEEE Access Trong-Thuc Hoang, Ckristian Duran, Duc-Thinh Nguyen-Hoang, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2020	C	`conf`	Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors. ISCAS Ckristian Duran, Hanssel Morales, Camilo Rojas, Annachiara Ruospo, Ernesto Sánchez, Elkim Roa
2019	—	`conf`	A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller. LASCAS Hanssel Morales, Ckristian Duran, Elkim Roa
2019	J	`jnl`	Defeating Silicon Reverse Engineering Using a Layout-Level Standard Cell Camouflage. IEEE Trans. Consumer Electron. Héctor Gómez, Ckristian Duran, Elkim Roa
2018	C	`conf`	Standard cell camouflage method to counter silicon reverse engineering. ICCE Héctor Gómez, Ckristian Duran, Elkim Roa
2016	—	`conf`	A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC. LASCAS Ckristian Duran, D. Luis Rueda, Giovanny Castillo, Anderson Agudelo, Camilo Rojas, Luis Chaparro, Harry Hurtado, Juan Romero, Wilmer Ramirez, Héctor Gómez, Javier Ardila, Luis E. Rueda G., Hugo Hernandez, Jose Amaya, Elkim Roa