Ciprian Seiculescu

18 papers A* 2A 2C 1Misc 2Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2022 Misc conf
Benchmarking TensorFlow Lite Quantization Algorithms for Deep Neural Networks.
SACI
Ioan Lucan Orasan, Ciprian Seiculescu, Catalin-Daniel Caleanu
2022 — conf
Evaluation of Tracking Algorithms for Contrast Enhanced Ultrasound Imaging Exploration.
ACSW
Cristina Laura Sîrbu, Ciprian Seiculescu, Ghita Adrian Burdan, Tudor Moga, Catalin-Daniel Caleanu
2013 C conf
3.5-D integration: A case study.
ISCAS
Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Ciprian Seiculescu, Vasilis F. Pavlidis, Giovanni De Micheli
2013 J jnl
Designing best effort networks-on-chip to meet hard latency constraints.
ACM Trans. Embed. Comput. Syst.
Ciprian Seiculescu, Dara Rahmati, Srinivasan Murali, Hamid Sarbazi-Azad, Luca Benini, Giovanni De Micheli
2012 Misc conf
A distributed interleaving scheme for efficient access to WideIO DRAM memory.
CODES+ISSS
Ciprian Seiculescu, Luca Benini, Giovanni De Micheli
2012 — conf
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers.
NOCS
Stavros Volos, Ciprian Seiculescu, Boris Grot, Naser Khosro Pour, Babak Falsafi, Giovanni De Micheli
2012 — —
Design Methods and Tools for Application-Specific Predictable Networks-on-Chip.
Ciprian Seiculescu
2011 — ch.
3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks.
3D Integration for NoC-based SoC Architectures
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2011 — conf
A DRAM Centric NoC Architecture and Topology Design Approach.
ISVLSI
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2011 — ch.
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.
Low Power Networks-on-Chip
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2010 A conf
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.
DATE
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2010 J jnl
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands.
IEEE Trans. Circuits Syst. II Express Briefs
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2010 A* conf
Networks on Chips: from research to products.
DAC
Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini
2010 J jnl
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2009 — conf
A floorplan-aware interactive tool flow for NoC design and synthesis.
SoCC
Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini
2009 A* conf
NoC topology synthesis for supporting shutdown of voltage islands in SoCs.
DAC
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2009 A conf
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.
DATE
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2009 — conf
Synthesis of networks on chips for 3D systems on chips.
ASP-DAC
Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli